698 lines
17 KiB
Go
698 lines
17 KiB
Go
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// Copyright 2017 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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// This functionality requires MPSSE.
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//
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// Interfacing SPI:
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// http://www.ftdichip.com/Support/Documents/AppNotes/AN_114_FTDI_Hi_Speed_USB_To_SPI_Example.pdf
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//
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// Implementation based on
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// http://www.ftdichip.com/Support/Documents/AppNotes/AN_180_FT232H%20MPSSE%20Example%20-%20USB%20Current%20Meter%20using%20the%20SPI%20interface.pdf
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package ftdi
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import (
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"context"
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"errors"
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"fmt"
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"periph.io/x/conn/v3"
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"periph.io/x/conn/v3/gpio"
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"periph.io/x/conn/v3/physic"
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"periph.io/x/conn/v3/spi"
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)
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// spiMPSEEPort is an SPI port over a FTDI device in MPSSE mode using the data
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// command on the AD bus.
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type spiMPSEEPort struct {
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c spiMPSEEConn
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// Mutable.
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maxFreq physic.Frequency
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}
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func (s *spiMPSEEPort) Close() error {
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s.c.f.mu.Lock()
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s.c.f.usingSPI = false
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s.maxFreq = 0
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s.c.edgeInvert = false
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s.c.clkActiveLow = false
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s.c.noCS = false
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s.c.lsbFirst = false
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s.c.halfDuplex = false
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s.c.f.mu.Unlock()
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return nil
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}
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func (s *spiMPSEEPort) String() string {
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return s.c.f.String()
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}
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// Connect implements spi.Port.
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func (s *spiMPSEEPort) Connect(f physic.Frequency, m spi.Mode, bits int) (spi.Conn, error) {
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if f > physic.GigaHertz {
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return nil, fmt.Errorf("d2xx: invalid speed %s; maximum supported clock is 30MHz", f)
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}
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if f > 30*physic.MegaHertz {
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// TODO(maruel): Figure out a way to communicate that the speed was lowered.
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// https://github.com/google/periph/issues/255
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f = 30 * physic.MegaHertz
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}
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if f < 100*physic.Hertz {
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return nil, fmt.Errorf("d2xx: invalid speed %s; minimum supported clock is 100Hz; did you forget to multiply by physic.MegaHertz?", f)
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}
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if bits&7 != 0 {
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return nil, errors.New("d2xx: bits must be multiple of 8")
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}
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if bits != 8 {
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return nil, errors.New("d2xx: implement bits per word above 8")
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}
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s.c.f.mu.Lock()
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defer s.c.f.mu.Unlock()
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s.c.noCS = m&spi.NoCS != 0
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s.c.halfDuplex = m&spi.HalfDuplex != 0
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s.c.lsbFirst = m&spi.LSBFirst != 0
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m &^= spi.NoCS | spi.HalfDuplex | spi.LSBFirst
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if s.c.halfDuplex {
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return nil, errors.New("d2xx: spi.HalfDuplex is not yet supported (implementing wouldn't be too hard, please submit a PR")
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}
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if m < 0 || m > 3 {
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return nil, errors.New("d2xx: unknown spi mode")
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}
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s.c.edgeInvert = m&1 != 0
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s.c.clkActiveLow = m&2 != 0
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if s.maxFreq == 0 || f < s.maxFreq {
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// TODO(maruel): We could set these only *during* the SPI operation, which
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// would make more sense.
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if _, err := s.c.f.h.MPSSEClock(f); err != nil {
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return nil, err
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}
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s.maxFreq = f
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}
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s.c.resetIdle()
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if err := s.c.f.h.MPSSEDBus(s.c.f.dbus.direction, s.c.f.dbus.value); err != nil {
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return nil, err
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}
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s.c.f.usingSPI = true
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return &s.c, nil
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}
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// LimitSpeed implements spi.Port.
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func (s *spiMPSEEPort) LimitSpeed(f physic.Frequency) error {
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if f > physic.GigaHertz {
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return fmt.Errorf("d2xx: invalid speed %s; maximum supported clock is 30MHz", f)
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}
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if f > 30*physic.MegaHertz {
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f = 30 * physic.MegaHertz
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}
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if f < 100*physic.Hertz {
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return errors.New("d2xx: minimum supported clock is 100Hz; did you forget to multiply by physic.MegaHertz?")
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}
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s.c.f.mu.Lock()
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defer s.c.f.mu.Unlock()
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if s.maxFreq != 0 && s.maxFreq <= f {
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return nil
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}
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s.maxFreq = f
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// TODO(maruel): We could set these only *during* the SPI operation, which
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// would make more sense.
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_, err := s.c.f.h.MPSSEClock(s.maxFreq)
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return err
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}
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// CLK returns the SCK (clock) pin.
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func (s *spiMPSEEPort) CLK() gpio.PinOut {
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return s.c.CLK()
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}
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// MOSI returns the SDO (master out, slave in) pin.
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func (s *spiMPSEEPort) MOSI() gpio.PinOut {
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return s.c.MOSI()
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}
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// MISO returns the SDI (master in, slave out) pin.
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func (s *spiMPSEEPort) MISO() gpio.PinIn {
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return s.c.MISO()
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}
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// CS returns the CSN (chip select) pin.
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func (s *spiMPSEEPort) CS() gpio.PinOut {
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return s.c.CS()
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}
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type spiMPSEEConn struct {
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// Immutable.
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f *FT232H
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// Initialized at Connect().
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edgeInvert bool // CPHA=1
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clkActiveLow bool // CPOL=1
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noCS bool // CS line is not changed
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lsbFirst bool // Default is MSB first
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halfDuplex bool // 3 wire mode
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}
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func (s *spiMPSEEConn) String() string {
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return s.f.String()
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}
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func (s *spiMPSEEConn) Tx(w, r []byte) error {
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var p = [1]spi.Packet{{W: w, R: r}}
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return s.TxPackets(p[:])
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}
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func (s *spiMPSEEConn) Duplex() conn.Duplex {
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// TODO(maruel): Support half if there's a need.
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return conn.Full
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}
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func (s *spiMPSEEConn) TxPackets(pkts []spi.Packet) error {
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// Verification.
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for _, p := range pkts {
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if p.KeepCS {
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return errors.New("d2xx: implement spi.Packet.KeepCS")
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}
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if p.BitsPerWord&7 != 0 {
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return errors.New("d2xx: bits must be a multiple of 8")
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}
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if p.BitsPerWord != 0 && p.BitsPerWord != 8 {
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return errors.New("d2xx: implement spi.Packet.BitsPerWord")
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}
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if err := verifyBuffers(p.W, p.R); err != nil {
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return err
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}
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}
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s.f.mu.Lock()
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defer s.f.mu.Unlock()
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const clk = byte(1) << 0
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const mosi = byte(1) << 1
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const miso = byte(1) << 2
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const cs = byte(1) << 3
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s.resetIdle()
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idle := s.f.dbus.value
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start1 := idle
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if !s.noCS {
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start1 &^= cs
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}
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// In mode 0 and 2, start2 is not needed.
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start2 := start1
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stop := idle
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if s.edgeInvert {
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// This is needed to 'prime' the clock.
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start2 ^= clk
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// With mode 1 and 3, keep the clock steady while CS is being deasserted to
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// not create a spurious clock.
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stop ^= clk
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}
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ew := gpio.FallingEdge
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er := gpio.RisingEdge
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if s.edgeInvert {
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ew, er = er, ew
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}
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if s.clkActiveLow {
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// TODO(maruel): Not sure.
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ew, er = er, ew
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}
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// FT232H claims 512 USB packet support, so to reduce the chatter over USB,
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// try to make all I/O be aligned on this amount. This also removes the need
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// for heap usage. The idea is to always trail reads by one buffer. This is
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// fine as the device has 1024 byte read buffer. Operations look like this:
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// W, W, R, W, R, W, R, R
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// This enables reducing the I/O gaps between USB packets as the device is
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// always busy with operations.
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var buf [512]byte
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cmd := buf[:0]
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keptCS := false
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// Loop, without increasing the index.
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for _, p := range pkts {
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if len(p.W) == 0 && len(p.R) == 0 {
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continue
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}
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// TODO(maruel): s.halfDuplex.
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if !keptCS {
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for i := 0; i < 5; i++ {
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cmd = append(cmd, gpioSetD, idle, s.f.dbus.direction)
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}
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for i := 0; i < 5; i++ {
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cmd = append(cmd, gpioSetD, start1, s.f.dbus.direction)
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}
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}
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if s.edgeInvert {
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// This is needed to 'prime' the clock.
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for i := 0; i < 5; i++ {
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cmd = append(cmd, gpioSetD, start2, s.f.dbus.direction)
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}
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}
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op := mpsseTxOp(len(p.W) != 0, len(p.R) != 0, ew, er, s.lsbFirst)
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// Do an I/O loop. We can mutate p here because it is a copy.
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// TODO(maruel): Have the pipeline cross the packet boundary.
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if len(p.W) == 0 {
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// Have the write buffer point to the read one. This saves from
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// allocating memory. The side effect is that it will write whatever
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// happened to be in the read buffer.
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p.W = p.R[:]
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}
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pendingRead := 0
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for len(p.W) != 0 {
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// op, sizelo, sizehi.
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chunk := len(buf) - 3 - len(cmd)
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if l := len(p.W); chunk > l {
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chunk = l
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}
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cmd = append(cmd, op, byte(chunk-1), byte((chunk-1)>>8))
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cmd = append(cmd, p.W[:chunk]...)
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p.W = p.W[chunk:]
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if _, err := s.f.h.WriteFast(cmd); err != nil {
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return err
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}
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cmd = buf[:0]
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// TODO(maruel): Read 62 bytes at a time?
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// Delay reading by 512 bytes.
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if pendingRead >= 512 {
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if len(p.R) != 0 {
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// Align reads on 512 bytes exactly, aligned on USB packet size.
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if _, err := s.f.h.ReadAll(context.Background(), p.R[:512]); err != nil {
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return err
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}
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p.R = p.R[512:]
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pendingRead -= 512
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}
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}
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pendingRead += chunk
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}
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// Do not forget to read whatever is pending.
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// TODO(maruel): Investigate if a flush helps.
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if len(p.R) != 0 {
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// Send a flush to not wait for data.
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cmd = append(cmd, flush)
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if _, err := s.f.h.WriteFast(cmd); err != nil {
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return err
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}
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cmd = buf[:0]
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if _, err := s.f.h.ReadAll(context.Background(), p.R); err != nil {
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return err
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}
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}
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// TODO(maruel): Inject this in the write if it fits (it will generally
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// do). That will save one USB I/O, which is not insignificant.
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keptCS = p.KeepCS
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if !keptCS {
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cmd = append(cmd, flush)
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for i := 0; i < 5; i++ {
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cmd = append(cmd, gpioSetD, stop, s.f.dbus.direction)
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}
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for i := 0; i < 5; i++ {
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cmd = append(cmd, gpioSetD, idle, s.f.dbus.direction)
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}
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if _, err := s.f.h.WriteFast(cmd); err != nil {
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return err
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}
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cmd = buf[:0]
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}
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}
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return nil
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}
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// CLK returns the SCK (clock) pin.
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func (s *spiMPSEEConn) CLK() gpio.PinOut {
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return s.f.D0
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}
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// MOSI returns the SDO (master out, slave in) pin.
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func (s *spiMPSEEConn) MOSI() gpio.PinOut {
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return s.f.D1
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}
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// MISO returns the SDI (master in, slave out) pin.
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func (s *spiMPSEEConn) MISO() gpio.PinIn {
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return s.f.D2
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}
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// CS returns the CSN (chip select) pin.
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func (s *spiMPSEEConn) CS() gpio.PinOut {
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return s.f.D3
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}
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// resetIdle sets D0~D3. D0, D1 and D3 are output but only touch D3 is CS is
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// used.
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func (s *spiMPSEEConn) resetIdle() {
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const clk = byte(1) << 0
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const mosi = byte(1) << 1
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const miso = byte(1) << 2
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const cs = byte(1) << 3
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if !s.noCS {
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s.f.dbus.direction &= 0xF0
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s.f.dbus.direction |= cs
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s.f.dbus.value &= 0xF0
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s.f.dbus.value |= cs
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} else {
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s.f.dbus.value &= 0xF8
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s.f.dbus.direction &= 0xF8
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}
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|
s.f.dbus.direction |= mosi | clk
|
||
|
|
if s.clkActiveLow {
|
||
|
|
// Clock idles high.
|
||
|
|
s.f.dbus.value |= clk
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
|
||
|
|
// spiSyncPort is an SPI port over a FTDI device in synchronous bit-bang mode.
|
||
|
|
type spiSyncPort struct {
|
||
|
|
c spiSyncConn
|
||
|
|
|
||
|
|
// Mutable.
|
||
|
|
maxFreq physic.Frequency
|
||
|
|
}
|
||
|
|
|
||
|
|
func (s *spiSyncPort) Close() error {
|
||
|
|
s.c.f.mu.Lock()
|
||
|
|
s.c.f.usingSPI = false
|
||
|
|
s.maxFreq = 0
|
||
|
|
s.c.edgeInvert = false
|
||
|
|
s.c.clkActiveLow = false
|
||
|
|
s.c.noCS = false
|
||
|
|
s.c.lsbFirst = false
|
||
|
|
s.c.halfDuplex = false
|
||
|
|
s.c.f.mu.Unlock()
|
||
|
|
return nil
|
||
|
|
}
|
||
|
|
|
||
|
|
func (s *spiSyncPort) String() string {
|
||
|
|
return s.c.f.String()
|
||
|
|
}
|
||
|
|
|
||
|
|
const ft232rMaxSpeed = 3 * physic.MegaHertz
|
||
|
|
|
||
|
|
// Connect implements spi.Port.
|
||
|
|
func (s *spiSyncPort) Connect(f physic.Frequency, m spi.Mode, bits int) (spi.Conn, error) {
|
||
|
|
if f > physic.GigaHertz {
|
||
|
|
return nil, fmt.Errorf("d2xx: invalid speed %s; maximum supported clock is 1.5MHz", f)
|
||
|
|
}
|
||
|
|
if f > ft232rMaxSpeed/2 {
|
||
|
|
// TODO(maruel): Figure out a way to communicate that the speed was lowered.
|
||
|
|
// https://github.com/google/periph/issues/255
|
||
|
|
f = ft232rMaxSpeed / 2
|
||
|
|
}
|
||
|
|
if f < 100*physic.Hertz {
|
||
|
|
return nil, fmt.Errorf("d2xx: invalid speed %s; minimum supported clock is 100Hz; did you forget to multiply by physic.MegaHertz?", f)
|
||
|
|
}
|
||
|
|
if bits&7 != 0 {
|
||
|
|
return nil, errors.New("d2xx: bits must be multiple of 8")
|
||
|
|
}
|
||
|
|
if bits != 8 {
|
||
|
|
return nil, errors.New("d2xx: implement bits per word above 8")
|
||
|
|
}
|
||
|
|
|
||
|
|
s.c.f.mu.Lock()
|
||
|
|
defer s.c.f.mu.Unlock()
|
||
|
|
s.c.noCS = m&spi.NoCS != 0
|
||
|
|
s.c.halfDuplex = m&spi.HalfDuplex != 0
|
||
|
|
s.c.lsbFirst = m&spi.LSBFirst != 0
|
||
|
|
m &^= spi.NoCS | spi.HalfDuplex | spi.LSBFirst
|
||
|
|
if s.c.halfDuplex {
|
||
|
|
return nil, errors.New("d2xx: spi.HalfDuplex is not yet supported (implementing wouldn't be too hard, please submit a PR")
|
||
|
|
}
|
||
|
|
if m < 0 || m > 3 {
|
||
|
|
return nil, errors.New("d2xx: unknown spi mode")
|
||
|
|
}
|
||
|
|
s.c.edgeInvert = m&1 != 0
|
||
|
|
s.c.clkActiveLow = m&2 != 0
|
||
|
|
if s.maxFreq == 0 || f < s.maxFreq {
|
||
|
|
if err := s.c.f.SetSpeed(f * 2); err != nil {
|
||
|
|
return nil, err
|
||
|
|
}
|
||
|
|
s.maxFreq = f
|
||
|
|
}
|
||
|
|
// D0, D2 and D3 are output. D4~D7 are kept as-is.
|
||
|
|
const mosi = byte(1) << 0 // TX
|
||
|
|
const miso = byte(1) << 1 // RX
|
||
|
|
const clk = byte(1) << 2 // RTS
|
||
|
|
const cs = byte(1) << 3 // CTS
|
||
|
|
mask := mosi | clk | cs | (s.c.f.dmask & 0xF0)
|
||
|
|
if err := s.c.f.setDBusMaskLocked(mask); err != nil {
|
||
|
|
return nil, err
|
||
|
|
}
|
||
|
|
// TODO(maruel): Combine both following calls if possible. We'd shave off a
|
||
|
|
// few ms.
|
||
|
|
if !s.c.noCS {
|
||
|
|
// CTS/SPI_CS is active low.
|
||
|
|
if err := s.c.f.dbusSyncGPIOOutLocked(3, gpio.High); err != nil {
|
||
|
|
return nil, err
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if s.c.clkActiveLow {
|
||
|
|
// RTS/SPI_CLK is active low.
|
||
|
|
if err := s.c.f.dbusSyncGPIOOutLocked(2, gpio.High); err != nil {
|
||
|
|
return nil, err
|
||
|
|
}
|
||
|
|
}
|
||
|
|
s.c.f.usingSPI = true
|
||
|
|
return &s.c, nil
|
||
|
|
}
|
||
|
|
|
||
|
|
// LimitSpeed implements spi.Port.
|
||
|
|
func (s *spiSyncPort) LimitSpeed(f physic.Frequency) error {
|
||
|
|
if f > physic.GigaHertz {
|
||
|
|
return fmt.Errorf("d2xx: invalid speed %s; maximum supported clock is 1.5MHz", f)
|
||
|
|
}
|
||
|
|
if f < 100*physic.Hertz {
|
||
|
|
return fmt.Errorf("d2xx: invalid speed %s; minimum supported clock is 100Hz; did you forget to multiply by physic.MegaHertz?", f)
|
||
|
|
}
|
||
|
|
s.c.f.mu.Lock()
|
||
|
|
defer s.c.f.mu.Unlock()
|
||
|
|
if s.maxFreq != 0 && s.maxFreq <= f {
|
||
|
|
return nil
|
||
|
|
}
|
||
|
|
if err := s.c.f.SetSpeed(f * 2); err == nil {
|
||
|
|
s.maxFreq = f
|
||
|
|
}
|
||
|
|
return nil
|
||
|
|
}
|
||
|
|
|
||
|
|
// CLK returns the SCK (clock) pin.
|
||
|
|
func (s *spiSyncPort) CLK() gpio.PinOut {
|
||
|
|
return s.c.CLK()
|
||
|
|
}
|
||
|
|
|
||
|
|
// MOSI returns the SDO (master out, slave in) pin.
|
||
|
|
func (s *spiSyncPort) MOSI() gpio.PinOut {
|
||
|
|
return s.c.MOSI()
|
||
|
|
}
|
||
|
|
|
||
|
|
// MISO returns the SDI (master in, slave out) pin.
|
||
|
|
func (s *spiSyncPort) MISO() gpio.PinIn {
|
||
|
|
return s.c.MISO()
|
||
|
|
}
|
||
|
|
|
||
|
|
// CS returns the CSN (chip select) pin.
|
||
|
|
func (s *spiSyncPort) CS() gpio.PinOut {
|
||
|
|
return s.c.CS()
|
||
|
|
}
|
||
|
|
|
||
|
|
type spiSyncConn struct {
|
||
|
|
// Immutable.
|
||
|
|
f *FT232R
|
||
|
|
|
||
|
|
// Initialized at Connect().
|
||
|
|
edgeInvert bool // CPHA=1
|
||
|
|
clkActiveLow bool // CPOL=1
|
||
|
|
noCS bool // CS line is not changed
|
||
|
|
lsbFirst bool // Default is MSB first
|
||
|
|
halfDuplex bool // 3 wire mode
|
||
|
|
}
|
||
|
|
|
||
|
|
func (s *spiSyncConn) String() string {
|
||
|
|
return s.f.String()
|
||
|
|
}
|
||
|
|
|
||
|
|
func (s *spiSyncConn) Tx(w, r []byte) error {
|
||
|
|
var p = [1]spi.Packet{{W: w, R: r}}
|
||
|
|
return s.TxPackets(p[:])
|
||
|
|
}
|
||
|
|
|
||
|
|
func (s *spiSyncConn) Duplex() conn.Duplex {
|
||
|
|
// TODO(maruel): Support half if there's a need.
|
||
|
|
return conn.Full
|
||
|
|
}
|
||
|
|
|
||
|
|
func (s *spiSyncConn) TxPackets(pkts []spi.Packet) error {
|
||
|
|
// We need to 'expand' each bit 2 times * 8 bits, which leads
|
||
|
|
// to a 16x memory usage increase. Adds 5 samples before and after.
|
||
|
|
totalW := 0
|
||
|
|
totalR := 0
|
||
|
|
for _, p := range pkts {
|
||
|
|
if p.KeepCS {
|
||
|
|
return errors.New("d2xx: implement spi.Packet.KeepCS")
|
||
|
|
}
|
||
|
|
if p.BitsPerWord&7 != 0 {
|
||
|
|
return errors.New("d2xx: bits must be a multiple of 8")
|
||
|
|
}
|
||
|
|
if p.BitsPerWord != 0 && p.BitsPerWord != 8 {
|
||
|
|
return errors.New("d2xx: implement spi.Packet.BitsPerWord")
|
||
|
|
}
|
||
|
|
if err := verifyBuffers(p.W, p.R); err != nil {
|
||
|
|
return err
|
||
|
|
}
|
||
|
|
// TODO(maruel): Correctly calculate offsets.
|
||
|
|
if len(p.W) != 0 {
|
||
|
|
totalW += 2 * 8 * len(p.W)
|
||
|
|
}
|
||
|
|
if len(p.R) != 0 {
|
||
|
|
totalR += 2 * 8 * len(p.R)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Create a large, single chunk.
|
||
|
|
var we, re []byte
|
||
|
|
if totalW != 0 {
|
||
|
|
totalW += 10
|
||
|
|
we = make([]byte, 0, totalW)
|
||
|
|
}
|
||
|
|
if totalR != 0 {
|
||
|
|
totalR += 10
|
||
|
|
re = make([]byte, totalR)
|
||
|
|
}
|
||
|
|
const mosi = byte(1) << 0 // TX
|
||
|
|
const miso = byte(1) << 1 // RX
|
||
|
|
const clk = byte(1) << 2 // RTS
|
||
|
|
const cs = byte(1) << 3 // CTS
|
||
|
|
|
||
|
|
s.f.mu.Lock()
|
||
|
|
defer s.f.mu.Unlock()
|
||
|
|
|
||
|
|
// https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Data_transmission
|
||
|
|
|
||
|
|
csActive := s.f.dvalue & s.f.dmask & 0xF0
|
||
|
|
csIdle := csActive
|
||
|
|
if !s.noCS {
|
||
|
|
csIdle = csActive | cs
|
||
|
|
}
|
||
|
|
clkIdle := csActive
|
||
|
|
clkActive := clkIdle | clk
|
||
|
|
if s.clkActiveLow {
|
||
|
|
clkActive, clkIdle = clkIdle, clkActive
|
||
|
|
csIdle |= clk
|
||
|
|
}
|
||
|
|
// Start of tx; assert CS if needed.
|
||
|
|
we = append(we, csIdle, clkIdle, clkIdle, clkIdle, clkIdle)
|
||
|
|
for _, p := range pkts {
|
||
|
|
if len(p.W) == 0 && len(p.R) == 0 {
|
||
|
|
continue
|
||
|
|
}
|
||
|
|
// TODO(maruel): s.halfDuplex.
|
||
|
|
for _, b := range p.W {
|
||
|
|
for j := uint(0); j < 8; j++ {
|
||
|
|
// For each bit, handle clock phase and data phase.
|
||
|
|
bit := byte(0)
|
||
|
|
if !s.lsbFirst {
|
||
|
|
// MSBF
|
||
|
|
if b&(0x80>>j) != 0 {
|
||
|
|
bit = mosi
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
// LSBF
|
||
|
|
if b&(1<<j) != 0 {
|
||
|
|
bit = mosi
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if !s.edgeInvert {
|
||
|
|
// Mode0/2; CPHA=0
|
||
|
|
we = append(we, clkIdle|bit, clkActive|bit)
|
||
|
|
} else {
|
||
|
|
// Mode1/3; CPHA=1
|
||
|
|
we = append(we, clkActive|bit, clkIdle|bit)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// End of tx; deassert CS.
|
||
|
|
we = append(we, clkIdle, clkIdle, clkIdle, clkIdle, csIdle)
|
||
|
|
|
||
|
|
if err := s.f.txLocked(we, re); err != nil {
|
||
|
|
return err
|
||
|
|
}
|
||
|
|
|
||
|
|
// Extract data from re into r.
|
||
|
|
for _, p := range pkts {
|
||
|
|
// TODO(maruel): Correctly calculate offsets.
|
||
|
|
if len(p.W) == 0 && len(p.R) == 0 {
|
||
|
|
continue
|
||
|
|
}
|
||
|
|
// TODO(maruel): halfDuplex.
|
||
|
|
for i := range p.R {
|
||
|
|
// For each bit, read at the right data phase.
|
||
|
|
b := byte(0)
|
||
|
|
for j := 0; j < 8; j++ {
|
||
|
|
if re[5+i*8*2+j*2+1]&byte(1)<<1 != 0 {
|
||
|
|
if !s.lsbFirst {
|
||
|
|
// MSBF
|
||
|
|
b |= 0x80 >> uint(j)
|
||
|
|
} else {
|
||
|
|
// LSBF
|
||
|
|
b |= 1 << uint(j)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
p.R[i] = b
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return nil
|
||
|
|
}
|
||
|
|
|
||
|
|
// CLK returns the SCK (clock) pin.
|
||
|
|
func (s *spiSyncConn) CLK() gpio.PinOut {
|
||
|
|
return s.f.D2 // RTS
|
||
|
|
}
|
||
|
|
|
||
|
|
// MOSI returns the SDO (master out, slave in) pin.
|
||
|
|
func (s *spiSyncConn) MOSI() gpio.PinOut {
|
||
|
|
return s.f.D0 // TX
|
||
|
|
}
|
||
|
|
|
||
|
|
// MISO returns the SDI (master in, slave out) pin.
|
||
|
|
func (s *spiSyncConn) MISO() gpio.PinIn {
|
||
|
|
return s.f.D1 // RX
|
||
|
|
}
|
||
|
|
|
||
|
|
// CS returns the CSN (chip select) pin.
|
||
|
|
func (s *spiSyncConn) CS() gpio.PinOut {
|
||
|
|
return s.f.D3 // CTS
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
|
||
|
|
func verifyBuffers(w, r []byte) error {
|
||
|
|
if len(w) != 0 {
|
||
|
|
if len(r) != 0 {
|
||
|
|
if len(w) != len(r) {
|
||
|
|
return errors.New("d2xx: both buffers must have the same size")
|
||
|
|
}
|
||
|
|
}
|
||
|
|
// TODO(maruel): When the buffer is >64Kb, cut it in parts and do not
|
||
|
|
// request a flush. Still try to read though.
|
||
|
|
if len(w) > 65536 {
|
||
|
|
return errors.New("d2xx: maximum buffer size is 64Kb")
|
||
|
|
}
|
||
|
|
} else if len(r) != 0 {
|
||
|
|
// TODO(maruel): Remove, this is not a problem.
|
||
|
|
if len(r) > 65536 {
|
||
|
|
return errors.New("d2xx: maximum buffer size is 64Kb")
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return nil
|
||
|
|
}
|
||
|
|
|
||
|
|
var _ spi.PortCloser = &spiMPSEEPort{}
|
||
|
|
var _ spi.Conn = &spiMPSEEConn{}
|
||
|
|
var _ spi.PortCloser = &spiSyncPort{}
|
||
|
|
var _ spi.Conn = &spiSyncConn{}
|