208 lines
7.1 KiB
Go
208 lines
7.1 KiB
Go
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// Copyright 2016 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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package allwinner
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import (
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"errors"
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"fmt"
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"log"
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"time"
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)
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const (
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// 31:20 reserved
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// Set this bit to ‘1’ to make the internal read sample point with a delay of
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// half cycle of SPI_CLK. It is used in high speed read operation to reduce
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// the error caused by the time delay of SPI_CLK propagating between master
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// and slave.
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// 1 – delay internal read sample point
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// 0 – normal operation, do not delay internal read sample point
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spiR8HalfDelay spiR8Ctl = 1 << 19 // Master Sample Data Control
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spiR8TransmitPause spiR8Ctl = 1 << 18 // Transmit Pause Enable
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spiR8CSLevel spiR8Ctl = 1 << 17 // SS_LEVEL; Chip Select level
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spiR8CSManual spiR8Ctl = 1 << 16 // SS_CTRL; Do not switch CS automatically
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spiR8DiscardHash spiR8Ctl = 1 << 15 // DHB
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spiR8DummyBurst spiR8Ctl = 1 << 14 // DDB
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spiR8CS0 spiR8Ctl = 0 << 12 // SS; Which CS line to use. For SPI0 only
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spiR8CS1 spiR8Ctl = 1 << 12 //
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spiR8CS2 spiR8Ctl = 2 << 12 //
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spiR8CS3 spiR8Ctl = 3 << 12 //
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spiR8RapidsReadMode spiR8Ctl = 1 << 11 // RPSM
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spiR8ExchangeBurst spiR8Ctl = 1 << 10 // XCH
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spiR8RXFIFOReset spiR8Ctl = 1 << 9 // RXFIFO Reset; Write to reset the FIFO as empty
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spiR8TXFIFOReset spiR8Ctl = 1 << 8 // TXFIFO Reset; Write to reset the FIFO as empty
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spiR8CSBetweenBursts spiR8Ctl = 1 << 7 // SSCTL
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spiR8LSB spiR8Ctl = 1 << 6 // LMTF; MSB by default, LSB when set
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spiR8DDMA spiR8Ctl = 1 << 5 // DMAM; Use dedicated DMA if set, normal DMA otherwise
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spiR8CSActiveLow spiR8Ctl = 1 << 4 // SSPOL; CS line polarity
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spiR8ClkActiveLow spiR8Ctl = 1 << 3 // POL; Clock line polarity
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spiR8PHA spiR8Ctl = 1 << 2 // PHA; Phase 1 if set (leading edge for setup data)
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spiR8Master spiR8Ctl = 1 << 1 // MODE; Slave mode if not set
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spiR8Enable spiR8Ctl = 1 << 0 // EN; Enable mode
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)
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// SPI_CTL
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// R8: Page 153-155. Default: 0x0002001C
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type spiR8Ctl uint32
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// SPI_INTCTL
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// R8: Page 155-156.
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type spiR8IntCtl uint32
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const (
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spiR8ClearInterrupt spiR8IntStatus = 1 << 31 // Clear interrupt busy flag
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// 30:18 reserved
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spiR8InvalidSS spiR8IntStatus = 1 << 17 // SSI
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spiR8TC spiR8IntStatus = 1 << 16 // TC; Transfer Completed
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)
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// SPI_INT_STA
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// R8: Page 156-157.
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type spiR8IntStatus uint32
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const (
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// 31:13 reserved
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spiR8DMATX3Quarter spiR8DMACtl = 1 << 12 // TXFIFO 3/4 empty
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spiR8DMATX1Quarter spiR8DMACtl = 1 << 11 // TXFIFO 1/4 empty
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spiR8DMATXByte spiR8DMACtl = 1 << 10 // TXFIFO Not Full
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spiR8DMATXHalf spiR8DMACtl = 1 << 9 // TXFIFO 1/2 empty
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spiR8DMATXEmpty spiR8DMACtl = 1 << 8 // TXFIFO empty
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// 7:5 reserved
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spiR8DMARX3Quarter spiR8DMACtl = 1 << 4 // RXFIFO 3/4 empty
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spiR8DMARX1Quarter spiR8DMACtl = 1 << 3 // RXFIFO 1/4 empty
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spiR8DMARXByte spiR8DMACtl = 1 << 2 // RXFIFO Not Full
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spiR8DMARXHalf spiR8DMACtl = 1 << 1 // RXFIFO 1/2 empty
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spiR8DMARXEmpty spiR8DMACtl = 1 << 0 // RXFIFO empty
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)
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// SPI_DMACTL
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// R8: Page 158.
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type spiR8DMACtl uint32
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const (
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// 31:13 reserved
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spiR8DivRateSelect2 spiR8ClockCtl = 1 << 12 // DRS; Use spiDivXX if set, use mask otherwise
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spiR8Div2 spiR8ClockCtl = 0 << 8 // CDR1; Use divisor 2^(n+1)
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spiR8Div4 spiR8ClockCtl = 1 << 8 //
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spiR8Div8 spiR8ClockCtl = 2 << 8 //
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spiR8Div16 spiR8ClockCtl = 3 << 8 //
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spiR8Div32 spiR8ClockCtl = 4 << 8 //
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spiR8Div64 spiR8ClockCtl = 5 << 8 //
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spiR8Div128 spiR8ClockCtl = 6 << 8 //
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spiR8Div256 spiR8ClockCtl = 7 << 8 //
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spiR8Div512 spiR8ClockCtl = 8 << 8 //
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spiR8Div1024 spiR8ClockCtl = 9 << 8 //
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spiR8Div2048 spiR8ClockCtl = 10 << 8 //
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spiR8Div4096 spiR8ClockCtl = 11 << 8 //
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spiR8Div8192 spiR8ClockCtl = 12 << 8 //
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spiR8Div16384 spiR8ClockCtl = 13 << 8 //
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spiR8Div32768 spiR8ClockCtl = 14 << 8 //
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spiR8Div65536 spiR8ClockCtl = 15 << 8 //
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spiR8Div1Mask spiR8ClockCtl = 0xFF // CDR2; Use divisor 2*(n+1)
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)
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// SPI_CCTL
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// R8: Page 159.
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type spiR8ClockCtl uint32
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const (
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// 31:25 reserved
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spiR8FIFOTXShift = 16 // 0 to 64
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// 15:7 reserved
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spiR8FIFORXShift = 0 // 0 to 64
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)
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// SPI_FIFO_STA
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// R8: Page 160.
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type spiR8FIFOStatus uint32
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func (s spiR8FIFOStatus) tx() uint8 {
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return uint8((uint32(s) >> 16) & 127)
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}
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func (s spiR8FIFOStatus) rx() uint8 {
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return uint8(uint32(s) & 127)
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}
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// spiR8Group is the mapping of SPI registers for one SPI controller.
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// R8: Page 152-153.
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type spiR8Group struct {
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rx uint32 // 0x00 SPI_RX_DATA RX Data
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tx uint32 // 0x04 SPI_TX_DATA TX Data
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ctl spiR8Ctl // 0x08 SPI_CTL Control
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intCtl spiR8IntCtl // 0x0C SPI_INTCTL Interrupt Control
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status spiR8IntStatus // 0x10 SPI_ST Status
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dmaCtl spiR8DMACtl // 0x14 SPI_DMACTL DMA Control
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wait uint32 // 0x18 SPI_WAIT Clock Counter; 16 bits
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clockCtl spiR8ClockCtl // 0x1C SPI_CCTL Clock Rate Control
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burstCounter uint32 // 0x20 SPI_BC Burst Counter; 24 bits
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transmitCounter uint32 // 0x24 SPI_TC Transmit Counter; 24 bits
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fifoStatus spiR8FIFOStatus // 0x28 SPI_FIFO_STA FIFO Status
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reserved [(0x1000 - 0x02C) / 4]uint32
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}
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func (s *spiR8Group) setup() {
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s.intCtl = 0
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s.status = 0
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//s.dmaCtl = spiR8DMARXByte
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s.dmaCtl = 0
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s.wait = 2
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s.clockCtl = spiR8DivRateSelect2 | spiR8Div1024
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// spiR8DDMA
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s.ctl = spiR8CSManual | spiR8LSB | spiR8Master | spiR8Enable
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}
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// spiMap is the mapping of SPI registers.
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// R8: Page 152-153.
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type spiMap struct {
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groups [3]spiR8Group
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}
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// spi2Write do a write on SPI2_MOSI via polling.
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func spi2Write(w []byte) error {
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if drvDMA.clockMemory == nil || drvDMA.spiMemory == nil {
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return errors.New("subsystem not initialized")
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}
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// Make sure the source clock is disabled. Set it at 250kHz.
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//drvDMA.clockMemory.spi2Clk &^= clockSPIEnable
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drvDMA.clockMemory.spi2Clk |= clockSPIEnable
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drvDMA.clockMemory.spi2Clk = clockSPIDiv8a | clockSPIDiv12b
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ch := &drvDMA.spiMemory.groups[2]
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ch.setup()
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fmt.Printf("Setup done\n")
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for i := 0; i < len(w)/4; i++ {
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// TODO(maruel): Access it in 8bit mode.
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ch.tx = uint32(w[0])
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for ch.fifoStatus.tx() == 0 {
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log.Printf("Waiting for bit %# v\n", ch)
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time.Sleep(time.Second)
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}
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}
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fmt.Printf("Done\n")
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return nil
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}
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// spi2Read do a read on SPI2_MISO via polling.
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func spi2Read(r []byte) error {
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if drvDMA.clockMemory == nil || drvDMA.spiMemory == nil {
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return errors.New("subsystem not initialized")
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}
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// Make sure the source clock is disabled. Set it at 250kHz.
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//drvDMA.clockMemory.spi2Clk &^= clockSPIEnable
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drvDMA.clockMemory.spi2Clk |= clockSPIEnable
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drvDMA.clockMemory.spi2Clk = clockSPIDiv8a | clockSPIDiv12b
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ch := &drvDMA.spiMemory.groups[2]
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ch.setup()
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for i := 0; i < len(r)/4; i++ {
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ch.tx = 0
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for ch.status&spiR8TC == 0 {
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}
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// TODO(maruel): Access it in 8bit mode.
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r[i] = uint8(ch.rx)
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}
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fmt.Printf("Done\n")
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return nil
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}
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