129 lines
5.8 KiB
Go
129 lines
5.8 KiB
Go
// Copyright 2016 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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package allwinner
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import (
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"time"
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"periph.io/x/periph/host/cpu"
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)
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// ReadTime returns the time on a monotonic timer.
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//
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// It only works if allwinner-dma successfully loaded. Otherwise it returns 0.
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func ReadTime() time.Duration {
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if drvDMA.timerMemory == nil {
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return 0
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}
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v := uint64(drvDMA.timerMemory.counterHigh)<<32 | uint64(drvDMA.timerMemory.counterLow)
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if v == 0 {
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// BUG(maruel): Implement using AVS_CNT0_REG on A64.
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return 0
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}
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// BUG(maruel): Assumes that counterCtrl & timerPLL6 is not set.
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const tick = time.Microsecond / 24
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return time.Duration(v) * tick
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}
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// Nanospin spins the CPU without calling into the kernel code if possible.
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func Nanospin(t time.Duration) {
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start := ReadTime()
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if start == 0 {
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// Use the slow generic version.
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cpu.Nanospin(t)
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return
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}
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for ReadTime()-start < t {
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}
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}
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//
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const (
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// 31:3 reserved
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timerPLL6 timerCtrl = 2 << 1 // CONT64_CLK_SRC_SEL; OSC24M if not set;
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timerReadLatchEnable timerCtrl = 1 << 1 // CONT64_RLATCH_EN; 1 to latch the counter to the registers
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timerClear = 1 << 0 // CONT64_CLR_EN; clears the counter
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)
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// R8: Page 96
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type timerCtrl uint32
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// timerMap is the mapping of important registers across CPUs.
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type timerMap struct {
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reserved0 [0x80 / 4]uint32 //
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cntCtl timerCtrl // 0x80 AVS_CNT_CTL_REG AVS Control Register
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cnt0 uint32 // 0x84 AVS_CNT0_REG AVS Counter 0 Register
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cnt1 uint32 // 0x88 AVS_CNT1_REG AVS Counter 1 Register
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cndDrv uint32 // 0x8C AVS_CNT_DIV_REG AVS Divisor Register
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reserved1 [0x10 / 4]uint32 // On R8 only.
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counterCtrl timerCtrl // 0x0A0 COUNTER64_CTRL_REG 64-bit Counter control
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counterLow uint32 // 0x0A4 COUNTER64_LOW_REG 64-bit Counter low
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counterHigh uint32 // 0x0A8 COUNTER64_HI_REG 64-bit Counter high
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}
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// A64: Page 161.
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type timerMapA64 struct {
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reserved0 uint32 // 0x0 TMR_IRQ_EN_REG Timer IRQ Enable Register
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reserved1 uint32 // 0x4 TMR_IRQ_STA_REG Timer Status Register
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reserved2 uint32 // 0x10 TMR0_CTRL_REG Timer 0 Control Register
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reserved3 uint32 // 0x14 TMR0_INTV_VALUE_REG Timer 0 Interval Value Register
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reserved4 uint32 // 0x18 TMR0_CUR_VALUE_REG Timer 0 Current Value Register
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reserved5 uint32 // 0x20 TMR1_CTRL_REG Timer 1 Control Register
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reserved6 uint32 // 0x24 TMR1_INTV_VALUE_REG Timer 1 Interval Value Register
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reserved7 uint32 // 0x28 TMR1_CUR_VALUE_REG Timer 1 Current Value Register
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cntCtl timerCtrl // 0x80 AVS_CNT_CTL_REG AVS Control Register
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cnt0 uint32 // 0x84 AVS_CNT0_REG AVS Counter 0 Register
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cnt1 uint32 // 0x88 AVS_CNT1_REG AVS Counter 1 Register
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cndDrv uint32 // 0x8C AVS_CNT_DIV_REG AVS Divisor Register
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reserved8 uint32 // 0xA0 WDOG0_IRQ_EN_REG Watchdog 0 IRQ Enable Register
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reserved9 uint32 // 0xA4 WDOG0_IRQ_STA_REG Watchdog 0 Status Register
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reserved10 uint32 // 0xB0 WDOG0_CTRL_REG Watchdog 0 Control Register
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reserved11 uint32 // 0xB4 WDOG0_CFG_REG Watchdog 0 Configuration Register
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reserved12 uint32 // 0xB8 WDOG0_MODE_REG Watchdog 0 Mode Register
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}
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// R8: Page 85
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type timerMapR8 struct {
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reserved0 uint32 // 0x000 ASYNC_TMR_IRQ_EN_REG Timer IRQ Enable
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reserved1 uint32 // 0x004 ASYNC_TMR_IRQ_STAS_REG Timer Status
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reserved2 [2]uint32 // 0x008-0x00C
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reserved3 uint32 // 0x010 ASYNC_TMR0_CTRL_REG Timer 0 Control
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reserved4 uint32 // 0x014 ASYNC_TMR0_INTV_VALUE_REG Timer 0 Interval Value
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reserved5 uint32 // 0x018 ASYNC_TMR0_CURNT_VALUE_REG Timer 0 Current Value
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reserved6 uint32 // 0x01C
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reserved7 uint32 // 0x020 ASYNC_TMR1_CTRL_REG Timer 1 Control
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reserved8 uint32 // 0x024 ASYNC_TMR1_INTV_VALUE_REG Timer 1 Interval Value
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reserved9 uint32 // 0x028 ASYNC_TMR1_CURNT_VALUE_REG Timer 1 Current Value
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reserved10 uint32 // 0x02C
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reserved11 uint32 // 0x030 ASYNC_TMR2_CTRL_REG Timer 2 Control
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reserved12 uint32 // 0x034 ASYNC_TMR2_INTV_VALUE_REG Timer 2 Interval Value
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reserved13 uint32 // 0x038 ASYNC_TMR2_CURNT_VALUE_REG Timer 2 Current Value
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reserved14 uint32 // 0x03C
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reserved15 uint32 // 0x040 ASYNC_TMR3_CTRL_REG Timer 3 Control
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reserved16 uint32 // 0x044 ASYNC_TMR3_INTV_VALUE_REG Timer 3 Interval Value
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reserved17 [2]uint32 // 0x048-0x04C
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reserved18 uint32 // 0x050 ASYNC_TMR4_CTRL_REG Timer 4 Control
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reserved19 uint32 // 0x054 ASYNC_TMR4_INTV_VALUE_REG Timer 4 Interval Value
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reserved20 uint32 // 0x058 ASYNC_TMR4_CURNT_VALUE_REG Timer 4 Current Value
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reserved21 uint32 // 0x05C
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reserved22 uint32 // 0x060 ASYNC_TMR5_CTRL_REG Timer 5 Control
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reserved23 uint32 // 0x064 ASYNC_TMR5_INTV_VALUE_REG Timer 5 Interval Value
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reserved24 uint32 // 0x068 ASYNC_TMR5_CURNT_VALUE_REG Timer 5 Current Value
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reserved25 [5]uint32 // 0x06C-0x07C
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cntCtl timerCtrl // 0x080 AVS_CNT_CTL_REG AVS Control Register
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cnt0 uint32 // 0x084 AVS_CNT0_REG AVS Counter 0 Register
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cnt1 uint32 // 0x088 AVS_CNT1_REG AVS Counter 1 Register
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cndDiv uint32 // 0x08C AVS_CNT_DIVISOR_REG AVS Divisor
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reserved26 uint32 // 0x090 WDOG_CTRL_REG
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reserved27 uint32 // 0x094 WDOG_MODE_REG Watchdog Mode
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reserved28 [2]uint32 // 0x098-0x09C
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counterCtrl timerCtrl // 0x0A0 COUNTER64_CTRL_REG 64-bit Counter control
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counterLow uint32 // 0x0A4 COUNTER64_LOW_REG 64-bit Counter low
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counterHigh uint32 // 0x0A8 COUNTER64_HI_REG 64-bit Counter high
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reserved29 [0x94]uint32 // 0x0AC-0x13C
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reserved30 uint32 // 0x140 CPU_CFG_REG CPU configuration register
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}
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