1261 lines
40 KiB
Go
1261 lines
40 KiB
Go
// Copyright 2017 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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// The DMA controller can be used for two functionality:
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// - implement zero-CPU continuous PWM.
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// - bitbang a large stream of bits over a GPIO pin, for example for WS2812b
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// support.
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//
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// The way it works under the hood is that the bcm283x has two registers, one
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// to set a bit and one to clear a bit.
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//
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// Each pin using PWM will get its own DMA channel. Each channel writes a
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// stream of "set bit" followed by "clear bit".
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//
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// <--------------- PWM period --------------->
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// <-- Duty cycle -->
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// High __________________ ______
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// | | |
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// | | |
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// | | |
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// Low | |__________________________|
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// **************************************************
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// ^each * is a DMA cycle
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//
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// For each DMA cycle, a control block (size 32 bytes) sets or clears the bit.
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// Control blocks are chained together, with the last one looping back to the
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// first. The number of control blocks is:
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// # control block = frequency of the DMA channel / requested PWM frequency
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//
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// Important: those control blocks are allocated in the video memory. On a
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// Raspberry Pi, this can configured, with a default at 64 MB.
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// For each PWM signal, the memory usage is:
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// size = 32 * frequency of the DMA channel / requested PWM frequency
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// Example, for 1 Hz:
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// size = 32 * 200 000 / 1 = 6400000, so around 6MB
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//
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//
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// References
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//
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// Page 7:
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// " Software accessing RAM directly must use physical addresses (based at
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// 0x00000000). Software accessing RAM using the DMA engines must use bus
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// addresses (based at 0xC0000000) " ... to skip the L1 cache.
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//
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// " The BCM2835 DMA Controller provides a total of 16 DMA channels. Each
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// channel operates independently from the others and is internally arbitrated
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// onto one of the 3 system buses. This means that the amount of bandwidth that
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// a DMA channel may consume can be controlled by the arbiter settings. "
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//
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// The CPU has 16 DMA channels but only the first 7 (#0 to #6) can do strides.
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// 7~15 have half the bandwidth.
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//
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// References
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//
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// DMA channel allocation:
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// https://github.com/raspberrypi/linux/issues/1327
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//
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// DMA location:
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// https://www.raspberrypi.org/forums/viewtopic.php?f=71&t=19797
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package bcm283x
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import (
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"errors"
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"fmt"
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"log"
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"os"
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"strings"
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"time"
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"periph.io/x/periph"
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"periph.io/x/periph/conn/gpio/gpiostream"
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"periph.io/x/periph/conn/physic"
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"periph.io/x/periph/host/pmem"
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"periph.io/x/periph/host/videocore"
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)
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const (
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periphMask = 0x00FFFFFF
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periphBus = 0x7E000000
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// maxLite is the maximum transfer allowed by a lite channel.
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maxLite = 65535
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)
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// Pages 47-50
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type dmaStatus uint32
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const (
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dmaReset dmaStatus = 1 << 31 // RESET; Writing a 1 to this bit will reset the DMA
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dmaAbort dmaStatus = 1 << 30 // ABORT; Writing a 1 to this bit will abort the current DMA CB. The DMA will load the next CB and attempt to continue.
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dmaDisableDebug dmaStatus = 1 << 29 // DISDEBUG; When set to 1, the DMA will not stop when the debug pause signal is asserted.
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// When set to 1, the DMA will keep a tally of the AXI writes going out and
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// the write responses coming in. At the very end of the current DMA transfer
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// it will wait until the last outstanding write response has been received
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// before indicating the transfer is complete. Whilst waiting it will load
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// the next CB address (but will not fetch the CB), clear the active flag (if
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// the next CB address = zero), and it will defer setting the END flag or the
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// INT flag until the last outstanding write response has been received.
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// In this mode, the DMA will pause if it has more than 13 outstanding writes
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// at any one time.
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dmaWaitForOutstandingWrites dmaStatus = 1 << 28 // WAIT_FOR_OUTSTANDING_WRITES
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// 27:24 reserved
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// 23:20 Lowest has higher priority on AXI.
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dmaPanicPriorityShift = 20
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dmaPanicPriorityMask = 0xF << 20 // PANIC_PRIORITY
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// 19:16 Lowest has higher priority on AXI.
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dmaPriorityShift = 16
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dmaPriorityMask = 0xF << dmaPriorityShift // PRIORITY
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// 15:9 reserved
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dmaErrorStatus dmaStatus = 1 << 8 // ERROR DMA error was detected; must be cleared manually.
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// 7 reserved
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dmaWaitingForOutstandingWrites dmaStatus = 1 << 6 // WAITING_FOR_OUTSTANDING_WRITES; Indicates if the DMA is currently waiting for any outstanding writes to be received, and is not transferring data.
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dmaDreqStopsDMA dmaStatus = 1 << 5 // DREQ_STOPS_DMA; Indicates if the DMA is currently paused and not transferring data due to the DREQ being inactive.
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// Indicates if the DMA is currently paused and not transferring data. This
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// will occur if: the active bit has been cleared, if the DMA is currently
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// executing wait cycles or if the debug_pause signal has been set by the
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// debug block, or the number of outstanding writes has exceeded the max
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// count.
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dmaPaused dmaStatus = 1 << 4 // PAUSED
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// Indicates the state of the selected DREQ (Data Request) signal, ie. the
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// DREQ selected by the PERMAP field of the transfer info.
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// 1 = Requesting data. This will only be valid once the DMA has started and
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// the PERMAP field has been loaded from the CB. It will remain valid,
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// indicating the selected DREQ signal, until a new CB is loaded. If
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// PERMAP is set to zero (unpaced transfer) then this bit will read back
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// as 1.
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// 0 = No data request.
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dmaDreq dmaStatus = 1 << 3 // DREQ
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// This is set when the transfer for the CB ends and INTEN is set to 1. Once
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// set it must be manually cleared down, even if the next CB has INTEN = 0.
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// Write 1 to clear.
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dmaInterrupt dmaStatus = 1 << 2 // INT
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// Set when the transfer described by the current control block is complete.
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// Write 1 to clear.
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dmaEnd dmaStatus = 1 << 1 // END
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// This bit enables the DMA. The DMA will start if this bit is set and the
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// CB_ADDR is non zero. The DMA transfer can be paused and resumed by
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// clearing, then setting it again.
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// This bit is automatically cleared at the end of the complete DMA transfer,
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// ie. after a NEXTCONBK = 0x0000_0000 has been loaded.
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dmaActive dmaStatus = 1 << 0 // ACTIVE
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)
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var dmaStatusMap = []struct {
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v dmaStatus
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s string
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}{
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{dmaReset, "Reset"},
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{dmaAbort, "Abort"},
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{dmaDisableDebug, "DisableDebug"},
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{dmaWaitForOutstandingWrites, "WaitForOutstandingWrites"},
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{dmaErrorStatus, "ErrorStatus"},
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{dmaWaitingForOutstandingWrites, "WaitingForOutstandingWrites"},
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{dmaDreqStopsDMA, "DreqStopsDMA"},
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{dmaPaused, "Paused"},
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{dmaDreq, "Dreq"},
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{dmaInterrupt, "Interrupt"},
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{dmaEnd, "End"},
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{dmaActive, "Active"},
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}
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func (d dmaStatus) String() string {
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var out []string
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for _, l := range dmaStatusMap {
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if d&l.v != 0 {
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d &^= l.v
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out = append(out, l.s)
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}
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}
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if v := d & dmaPanicPriorityMask; v != 0 {
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out = append(out, fmt.Sprintf("pp%d", v>>dmaPanicPriorityShift))
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d &^= dmaPanicPriorityMask
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}
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if v := d & dmaPriorityMask; v != 0 {
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out = append(out, fmt.Sprintf("p%d", v>>dmaPriorityShift))
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d &^= dmaPriorityMask
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}
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if d != 0 {
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out = append(out, fmt.Sprintf("dmaStatus(0x%x)", uint32(d)))
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}
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if len(out) == 0 {
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return "0"
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}
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return strings.Join(out, "|")
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}
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// Pages 50-52
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type dmaTransferInfo uint32
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const (
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// 31:27 reserved
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// Don't do wide writes as 2 beat burst; only for channels 0 to 6
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dmaNoWideBursts dmaTransferInfo = 1 << 26 // NO_WIDE_BURSTS
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// 25:21 Slows down the DMA throughput by setting the number of dummy cycles
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// burnt after each DMA read or write is completed.
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dmaWaitCyclesShift = 21
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dmaWaitcyclesMax = 0x1F
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dmaWaitCyclesMask dmaTransferInfo = dmaWaitcyclesMax << dmaWaitCyclesShift // WAITS
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// 20:16 Peripheral mapping (1-31) whose ready signal shall be used to
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// control the rate of the transfers. 0 means continuous un-paced transfer.
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//
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// It is the source used to pace the data reads and writes operations, each
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// pace being a DReq (Data Request).
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//
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// Page 61
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dmaPerMapShift = 16
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dmaPerMapMask dmaTransferInfo = 31 << dmaPerMapShift
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dmaFire dmaTransferInfo = 0 << dmaPerMapShift // PERMAP; Continuous trigger
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dmaDSI dmaTransferInfo = 1 << dmaPerMapShift // Display Serial Interface (?)
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dmaPCMTX dmaTransferInfo = 2 << dmaPerMapShift //
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dmaPCMRX dmaTransferInfo = 3 << dmaPerMapShift //
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dmaSMI dmaTransferInfo = 4 << dmaPerMapShift // Secondary Memory Interface (?)
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dmaPWM dmaTransferInfo = 5 << dmaPerMapShift //
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dmaSPITX dmaTransferInfo = 6 << dmaPerMapShift //
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dmaSPIRX dmaTransferInfo = 7 << dmaPerMapShift //
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dmaBscSPIslaveTX dmaTransferInfo = 8 << dmaPerMapShift //
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dmaBscSPIslaveRX dmaTransferInfo = 9 << dmaPerMapShift //
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dmaUnused dmaTransferInfo = 10 << dmaPerMapShift //
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dmaEMMC dmaTransferInfo = 11 << dmaPerMapShift //
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dmaUARTTX dmaTransferInfo = 12 << dmaPerMapShift //
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dmaSDHost dmaTransferInfo = 13 << dmaPerMapShift //
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dmaUARTRX dmaTransferInfo = 14 << dmaPerMapShift //
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dmaDSI2 dmaTransferInfo = 15 << dmaPerMapShift // Same as DSI
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dmaSlimBusMCTX dmaTransferInfo = 16 << dmaPerMapShift //
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dmaHDMI dmaTransferInfo = 17 << dmaPerMapShift // 216MHz; potentially a (216MHz/(26+1)) 8MHz copy rate but it fails if HDMI is disabled
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dmaSlimBusMCRX dmaTransferInfo = 18 << dmaPerMapShift //
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dmaSlimBusDC0 dmaTransferInfo = 19 << dmaPerMapShift //
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dmaSlimBusDC1 dmaTransferInfo = 20 << dmaPerMapShift //
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dmaSlimBusDC2 dmaTransferInfo = 21 << dmaPerMapShift //
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dmaSlimBusDC3 dmaTransferInfo = 22 << dmaPerMapShift //
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dmaSlimBusDC4 dmaTransferInfo = 23 << dmaPerMapShift //
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dmaScalerFIFO0 dmaTransferInfo = 24 << dmaPerMapShift // Also on SMI; SMI can be disabled with smiDisable
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dmaScalerFIFO1 dmaTransferInfo = 25 << dmaPerMapShift //
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dmaScalerFIFO2 dmaTransferInfo = 26 << dmaPerMapShift //
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dmaSlimBusDC5 dmaTransferInfo = 27 << dmaPerMapShift //
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dmaSlimBusDC6 dmaTransferInfo = 28 << dmaPerMapShift //
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dmaSlimBusDC7 dmaTransferInfo = 29 << dmaPerMapShift //
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dmaSlimBusDC8 dmaTransferInfo = 30 << dmaPerMapShift //
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dmaSlimBusDC9 dmaTransferInfo = 31 << dmaPerMapShift //
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dmaBurstLengthShift = 12
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dmaBurstLengthMask dmaTransferInfo = 0xF << dmaBurstLengthShift // BURST_LENGTH 15:12 0 means a single transfer.
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dmaSrcIgnore dmaTransferInfo = 1 << 11 // SRC_IGNORE Source won't be read, output will be zeros.
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dmaSrcDReq dmaTransferInfo = 1 << 10 // SRC_DREQ
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dmaSrcWidth128 dmaTransferInfo = 1 << 9 // SRC_WIDTH 128 bits reads if set, 32 bits otherwise.
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dmaSrcInc dmaTransferInfo = 1 << 8 // SRC_INC Increment read pointer by 32/128bits at each read if set.
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dmaDstIgnore dmaTransferInfo = 1 << 7 // DEST_IGNORE Do not write.
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dmaDstDReq dmaTransferInfo = 1 << 6 // DEST_DREQ
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dmaDstWidth128 dmaTransferInfo = 1 << 5 // DEST_WIDTH 128 bits writes if set, 32 bits otherwise.
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dmaDstInc dmaTransferInfo = 1 << 4 // DEST_INC Increment write pointer by 32/128bits at each read if set.
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dmaWaitResp dmaTransferInfo = 1 << 3 // WAIT_RESP DMA waits for AXI write response.
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// 2 reserved
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// 2D mode interpret of txLen; linear if unset; only for channels 0 to 6.
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dmaTransfer2DMode dmaTransferInfo = 1 << 1 // TDMODE
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dmaInterruptEnable dmaTransferInfo = 1 << 0 // INTEN Generate an interrupt upon completion.
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)
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var dmaTransferInfoMap = []struct {
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v dmaTransferInfo
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s string
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}{
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{dmaNoWideBursts, "NoWideBursts"},
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{dmaSrcIgnore, "SrcIgnore"},
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{dmaSrcDReq, "SrcDReq"},
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{dmaSrcWidth128, "SrcWidth128"},
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{dmaSrcInc, "SrcInc"},
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{dmaDstIgnore, "DstIgnore"},
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{dmaDstDReq, "DstDReq"},
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{dmaDstWidth128, "DstWidth128"},
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{dmaDstInc, "DstInc"},
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{dmaWaitResp, "WaitResp"},
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{dmaTransfer2DMode, "Transfer2DMode"},
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{dmaInterruptEnable, "InterruptEnable"},
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}
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var dmaPerMap = []string{
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"Fire",
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"DSI",
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"PCMTX",
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"PCMRX",
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"SMI",
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"PWM",
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"SPITX",
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"SPIRX",
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"BscSPISlaveTX",
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"BscSPISlaveRX",
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"Unused",
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"EMMC",
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"UARTTX",
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"SDHOST",
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"UARTRX",
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"DSI2",
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"SlimBusMCTX",
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"HDMI",
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"SlimBusMCRX",
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"SlimBusDC0",
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"SlimBusDC1",
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"SlimBusDC2",
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"SlimBusDC3",
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"SlimBusDC4",
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"ScalerFIFO0",
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"ScalerFIFO1",
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"ScalerFIFO2",
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"SlimBusDC5",
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"SlimBusDC6",
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"SlimBusDC7",
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"SlimBusDC8",
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"SlimBusDC9",
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}
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func (d dmaTransferInfo) String() string {
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var out []string
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for _, l := range dmaTransferInfoMap {
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if d&l.v != 0 {
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d &^= l.v
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out = append(out, l.s)
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}
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}
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if v := d & dmaWaitCyclesMask; v != 0 {
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out = append(out, fmt.Sprintf("waits=%d", v>>dmaWaitCyclesShift))
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d &^= dmaWaitCyclesMask
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}
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if v := d & dmaBurstLengthMask; v != 0 {
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out = append(out, fmt.Sprintf("burst=%d", v>>dmaBurstLengthShift))
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d &^= dmaBurstLengthMask
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}
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out = append(out, dmaPerMap[(d&dmaPerMapMask)>>dmaPerMapShift])
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d &^= dmaPerMapMask
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if d != 0 {
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out = append(out, fmt.Sprintf("dmaTransferInfo(0x%x)", uint32(d)))
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}
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return strings.Join(out, "|")
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}
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// Page 55
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type dmaDebug uint32
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const (
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// 31:29 reserved
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dmaLite dmaDebug = 1 << 28 // LITE RO set for lite DMA controllers
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// 27:25 version
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dmaVersionShift = 25
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dmaVersionMask dmaDebug = 7 << dmaVersionShift // VERSION
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// 24:16 dmaState
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dmaStateShift = 16
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dmaStateMask dmaDebug = 0x1FF << dmaStateShift // DMA_STATE; the actual states are not documented
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// 15:8 dmaID
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dmaIDShift = 8
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dmaIDMask = 0xFF << dmaIDShift // DMA_ID; the index of the DMA controller
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// 7:4 outstandingWrites
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dmaOutstandingWritesShift = 4
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dmaOutstandingWritesMask = 0xF << dmaOutstandingWritesShift // OUTSTANDING_WRITES
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// 3 reserved
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dmaReadError dmaDebug = 1 << 2 // READ_ERROR slave read error; clear by writing a 1
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dmaFIFOError dmaDebug = 1 << 1 // FIF_ERROR fifo error; clear by writing a 1
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dmaReadLastNotSetError dmaDebug = 1 << 0 // READ_LAST_NOT_SET_ERROR last AXI read signal was not set when expected
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)
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var dmaDebugMap = []struct {
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v dmaDebug
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s string
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}{
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{dmaLite, "Lite"},
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{dmaReadError, "ReadError"},
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{dmaFIFOError, "FIFOError"},
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{dmaReadLastNotSetError, "ReadLastNotSetError"},
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}
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func (d dmaDebug) String() string {
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var out []string
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for _, l := range dmaDebugMap {
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if d&l.v != 0 {
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d &^= l.v
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out = append(out, l.s)
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}
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}
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if v := d & dmaVersionMask; v != 0 {
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out = append(out, fmt.Sprintf("v%d", uint32(v>>dmaVersionShift)))
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d &^= dmaVersionMask
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}
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if v := d & dmaStateMask; v != 0 {
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out = append(out, fmt.Sprintf("state(%x)", uint32(v>>dmaStateShift)))
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d &^= dmaStateMask
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}
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if v := d & dmaIDMask; v != 0 {
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out = append(out, fmt.Sprintf("#%x", uint32(v>>dmaIDShift)))
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d &^= dmaIDMask
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}
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if v := d & dmaOutstandingWritesMask; v != 0 {
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out = append(out, fmt.Sprintf("OutstandingWrites=%d", uint32(v>>dmaOutstandingWritesShift)))
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d &^= dmaOutstandingWritesMask
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}
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if d != 0 {
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out = append(out, fmt.Sprintf("dmaDebug(0x%x)", uint32(d)))
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}
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if len(out) == 0 {
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return "0"
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}
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return strings.Join(out, "|")
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}
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// 31:30 0
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// 29:16 yLength (only for channels #0 to #6)
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// 15:0 xLength
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type dmaTransferLen uint32
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// 31:16 dstStride byte increment to apply at the end of each row in 2D mode
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// 15:0 srcStride byte increment to apply at the end of each row in 2D mode
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type dmaStride uint32
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func (d dmaStride) String() string {
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y := (d >> 16) & 0xFFFF
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if y != 0 {
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return fmt.Sprintf("0x%x,0x%x", uint32(y), uint32(d&0xFFFF))
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}
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return fmt.Sprintf("0x%x", uint32(d&0xFFFF))
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}
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// controlBlock is 256 bits (32 bytes) in length.
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//
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// https://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
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// Page 40.
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type controlBlock struct {
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transferInfo dmaTransferInfo // 0x00 TI
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srcAddr uint32 // 0x04 SOURCE_AD pointer to source in physical address space
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dstAddr uint32 // 0x08 DEST_AD pointer to destination in physical address space
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txLen dmaTransferLen // 0x0C TXFR_LEN length in bytes
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stride dmaStride // 0x10 STRIDE
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// Pointer to the next chained controlBlock; must be 32 bytes aligned.
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// Set it to 0 to stop.
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nextCB uint32 // 0x14 NEXTCONBK
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reserved [2]uint32 // 0x18+0x1C
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}
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const (
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controlBlockSize = 32
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uint32Size = 4
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)
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// initBlock initializes a controlBlock for any valid DMA operation.
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//
|
|
// l is in bytes, not in words.
|
|
//
|
|
// dreq can be dmaFire, dmaPwm, dmaPcmTx, etc. waits is additional wait state
|
|
// between clocks.
|
|
func (c *controlBlock) initBlock(srcAddr, dstAddr, l uint32, srcIO, dstIO, srcInc, dstInc bool, dreq dmaTransferInfo) error {
|
|
if srcIO && dstIO {
|
|
return errors.New("only one of src and dst can be I/O")
|
|
}
|
|
if srcAddr == 0 && dstAddr == 0 {
|
|
return errors.New("at least one source or destination is required")
|
|
}
|
|
if srcAddr == 0 && srcIO {
|
|
return errors.New("using src as I/O requires src")
|
|
}
|
|
if dstAddr == 0 && dstIO {
|
|
return errors.New("using dst as I/O requires dst")
|
|
}
|
|
if dreq&^dmaPerMapMask != 0 {
|
|
return errors.New("dreq must be one of the clock source, nothing else")
|
|
}
|
|
|
|
t := dmaNoWideBursts | dmaWaitResp
|
|
if srcAddr == 0 {
|
|
t |= dmaSrcIgnore
|
|
c.srcAddr = 0
|
|
} else {
|
|
if srcIO {
|
|
// Memory mapped register
|
|
c.srcAddr = physToBus(srcAddr)
|
|
} else {
|
|
// Normal memory
|
|
c.srcAddr = physToUncachedPhys(srcAddr)
|
|
}
|
|
if srcInc {
|
|
t |= dmaSrcInc
|
|
}
|
|
}
|
|
if dstAddr == 0 {
|
|
t |= dmaDstIgnore
|
|
c.dstAddr = 0
|
|
} else {
|
|
if dstIO {
|
|
// Memory mapped register
|
|
c.dstAddr = physToBus(dstAddr)
|
|
} else {
|
|
// Normal memory
|
|
c.dstAddr = physToUncachedPhys(dstAddr)
|
|
}
|
|
if dstInc {
|
|
t |= dmaDstInc
|
|
}
|
|
}
|
|
if dreq != dmaFire {
|
|
// Inserting a wait prevents multiple transfers in a single DReq cycle.
|
|
waits := 1
|
|
t |= dreq | dmaTransferInfo(waits<<dmaWaitCyclesShift)
|
|
if srcIO {
|
|
t |= dmaSrcDReq
|
|
}
|
|
if dstIO {
|
|
t |= dmaDstDReq
|
|
}
|
|
}
|
|
c.transferInfo = t
|
|
c.txLen = dmaTransferLen(l)
|
|
c.stride = 0
|
|
c.nextCB = 0
|
|
return nil
|
|
}
|
|
|
|
func (c *controlBlock) GoString() string {
|
|
return fmt.Sprintf(
|
|
"{\n transferInfo: %s,\n srcAddr: 0x%x,\n dstAddr: 0x%x,\n txLen: %d,\n stride: %s,\n nextCB: 0x%x,\n}",
|
|
&c.transferInfo, c.srcAddr, c.dstAddr, c.txLen, &c.stride, c.nextCB)
|
|
}
|
|
|
|
// DMAChannel is the memory mapped registers for one DMA channel.
|
|
//
|
|
// Page 39.
|
|
type dmaChannel struct {
|
|
cs dmaStatus // 0x00 CS
|
|
cbAddr uint32 // 0x04 CONNBLK_AD *controlBlock in physical address space; rounded to 32 bytes
|
|
transferInfo dmaTransferInfo // 0x08 TI (RO) Copyied by DMA on start from cbAddr
|
|
srcAddr uint32 // 0x0C SOURCE_AD (RO) Copyied by DMA on start from cbAddr
|
|
dstAddr uint32 // 0x10 DEST_AD (RO) Copyied by DMA on start from cbAddr
|
|
txLen dmaTransferLen // 0x14 TXFR_LEN (RO) Copyied by DMA on start from cbAddr
|
|
stride dmaStride // 0x18 STRIDE (RO) Copyied by DMA on start from cbAddr
|
|
nextCB uint32 // 0x1C NEXTCONBK Only safe to edit when DMA is paused
|
|
debug dmaDebug // 0x20 DEBUG
|
|
reserved [(0x100 - 0x24) / uint32Size]uint32 // 0x24
|
|
}
|
|
|
|
func (d *dmaChannel) isAvailable() bool {
|
|
return (d.cs&^dmaDreq) == 0 && d.cbAddr == 0
|
|
}
|
|
|
|
// reset resets the DMA channel in a way that makes it directly available.
|
|
//
|
|
// It doesn't clear the local controlBlock cached values.
|
|
func (d *dmaChannel) reset() {
|
|
d.cs = dmaReset
|
|
d.cbAddr = 0
|
|
}
|
|
|
|
// startIO initializes the DMA channel to start a transmission.
|
|
//
|
|
// The channel must have been reseted before.
|
|
func (d *dmaChannel) startIO(cb uint32) {
|
|
d.cbAddr = cb
|
|
d.cs = dmaWaitForOutstandingWrites | 8<<dmaPanicPriorityShift | 8<<dmaPriorityShift | dmaActive
|
|
}
|
|
|
|
// wait waits for a DMA channel transmission to complete.
|
|
//
|
|
// It must have started successfully before.
|
|
func (d *dmaChannel) wait() error {
|
|
// TODO(maruel): Calculate the number of bytes remaining, the clock rate and
|
|
// do a short sleep instead of a spin. To do so, it'll need the clock rate.
|
|
// Spin until the the bit is reset, to release the DMA controller channel.
|
|
for d.cs&dmaActive != 0 && d.debug&(dmaReadError|dmaFIFOError|dmaReadLastNotSetError) == 0 {
|
|
}
|
|
if d.debug&dmaReadError != 0 {
|
|
return errors.New("DMA read error")
|
|
}
|
|
if d.debug&dmaFIFOError != 0 {
|
|
return errors.New("DMA FIFO error")
|
|
}
|
|
if d.debug&dmaReadLastNotSetError != 0 {
|
|
return errors.New("DMA AIX read error")
|
|
}
|
|
return nil
|
|
}
|
|
|
|
func (d *dmaChannel) GoString() string {
|
|
return fmt.Sprintf(
|
|
"{\n cs: %s,\n cbAddr: 0x%x,\n transferInfo: %s,\n srcAddr: 0x%x,\n dstAddr: 0x%x,\n txLen: %v,\n stride: %s,\n nextCB: 0x%x,\n debug: %s,\n reserved: {...},\n}",
|
|
d.cs, d.cbAddr, d.transferInfo, d.srcAddr, d.dstAddr, d.txLen, d.stride, d.nextCB, d.debug)
|
|
}
|
|
|
|
// dmaMap is the block for the first 15 channels and control registers.
|
|
//
|
|
// Note that we modify the DMA controllers without telling the kernel driver.
|
|
// The driver keeps its own table of which DMA channel is available so this
|
|
// code could effectively crash the whole system. It practice this works.
|
|
// #everythingisfine
|
|
//
|
|
// Page 40.
|
|
type dmaMap struct {
|
|
channels [15]dmaChannel
|
|
padding0 [0xE0]byte //
|
|
intStatus uint32 // 0xFE0 INT_STATUS bits 15:0 mapped to controllers #15 to #0
|
|
padding1 [0xC]byte //
|
|
enable uint32 // 0xFF0 ENABLE bits 14:0 mapped to controllers #14 to #0
|
|
}
|
|
|
|
func indent(s, indent string) string {
|
|
var out []string
|
|
for _, x := range strings.Split(s, "\n") {
|
|
if len(x) != 0 {
|
|
out = append(out, indent+x)
|
|
} else {
|
|
out = append(out, "")
|
|
}
|
|
}
|
|
return strings.Join(out, "\n")
|
|
}
|
|
|
|
func (d *dmaMap) GoString() string {
|
|
out := []string{"{"}
|
|
for i := range d.channels {
|
|
out = append(out, indent(fmt.Sprintf("%d: %s", i, d.channels[i].GoString()+","), " "))
|
|
}
|
|
out = append(out, fmt.Sprintf(" intStatus: 0x%x,", d.intStatus))
|
|
out = append(out, fmt.Sprintf(" enable: 0x%x,", d.enable))
|
|
out = append(out, "}")
|
|
return strings.Join(out, "\n")
|
|
}
|
|
|
|
// pickChannel searches for a free DMA channel.
|
|
func pickChannel(blacklist ...int) (int, *dmaChannel) {
|
|
// Try the lite ones first.
|
|
if drvDMA.dmaMemory != nil {
|
|
// TODO(maruel): Trying to use channel #15 always fails.
|
|
/*
|
|
if drvDMA.dmaChannel15 != nil {
|
|
if drvDMA.dmaChannel15.isAvailable() {
|
|
drvDMA.dmaChannel15.reset()
|
|
return 15, drvDMA.dmaChannel15
|
|
}
|
|
}
|
|
*/
|
|
// TODO(maruel): May as well use a lookup table.
|
|
for i := len(drvDMA.dmaMemory.channels) - 1; i >= 0; i-- {
|
|
for _, exclude := range blacklist {
|
|
if i == exclude {
|
|
goto skip
|
|
}
|
|
}
|
|
if drvDMA.dmaMemory.channels[i].isAvailable() {
|
|
drvDMA.dmaMemory.channels[i].reset()
|
|
return i, &drvDMA.dmaMemory.channels[i]
|
|
}
|
|
skip:
|
|
}
|
|
}
|
|
// Uncomment to understand the state of the DMA channels.
|
|
//log.Printf("%#v", drvDMA.dmaMemory)
|
|
return -1, nil
|
|
}
|
|
|
|
// runIO picks a DMA channel, initialize it and runs a transfer.
|
|
//
|
|
// It tries to release the channel as soon as it can.
|
|
func runIO(pCB pmem.Mem, liteOk bool) error {
|
|
var blacklist []int
|
|
if !liteOk {
|
|
blacklist = []int{7, 8, 9, 10, 11, 12, 13, 14, 15}
|
|
}
|
|
_, ch := pickChannel(blacklist...)
|
|
if ch == nil {
|
|
return errors.New("bcm283x-dma: no channel available")
|
|
}
|
|
defer ch.reset()
|
|
ch.startIO(uint32(pCB.PhysAddr()))
|
|
return ch.wait()
|
|
}
|
|
|
|
func allocateCB(size int) ([]controlBlock, *videocore.Mem, error) {
|
|
buf, err := drvDMA.dmaBufAllocator((size + 0xFFF) &^ 0xFFF)
|
|
if err != nil {
|
|
return nil, nil, err
|
|
}
|
|
var cb []controlBlock
|
|
if err := buf.AsPOD(&cb); err != nil {
|
|
_ = buf.Close()
|
|
return nil, nil, err
|
|
}
|
|
return cb, buf, nil
|
|
}
|
|
|
|
// dmaWriteStreamPCM streams data to a PCM enabled pin as a half-duplex I²S
|
|
// channel.
|
|
func dmaWriteStreamPCM(p *Pin, w gpiostream.Stream) error {
|
|
d := w.Duration()
|
|
if d == 0 {
|
|
return nil
|
|
}
|
|
f := w.Frequency()
|
|
_, _, _, actualfreq, err := calcSource(f, 1)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
if actualfreq != f {
|
|
return errors.New("TODO(maruel): handle oversampling")
|
|
}
|
|
|
|
// Start clock earlier.
|
|
drvDMA.pcmMemory.reset()
|
|
_, _, err = setPCMClockSource(f)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
|
|
// Calculate the number of bytes needed.
|
|
l := (int(w.Frequency()/f) + 7) / 8 // Bytes
|
|
buf, err := drvDMA.dmaBufAllocator((l + 0xFFF) &^ 0xFFF)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer buf.Close()
|
|
if err := copyStreamToDMABuf(w, buf.Uint32()); err != nil {
|
|
return err
|
|
}
|
|
|
|
cb, pCB, err := allocateCB(4096)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer pCB.Close()
|
|
reg := drvDMA.pcmBaseAddr + 0x4 // pcmMap.fifo
|
|
if err = cb[0].initBlock(uint32(buf.PhysAddr()), reg, uint32(l), false, true, true, false, dmaPCMTX); err != nil {
|
|
return err
|
|
}
|
|
|
|
defer drvDMA.pcmMemory.reset()
|
|
// Start transfer
|
|
drvDMA.pcmMemory.set()
|
|
err = runIO(pCB, l <= maxLite)
|
|
// We have to wait PCM to be finished even after DMA finished.
|
|
for drvDMA.pcmMemory.cs&pcmTXErr == 0 {
|
|
Nanospin(10 * time.Nanosecond)
|
|
}
|
|
return err
|
|
}
|
|
|
|
func dmaWritePWMFIFO() (*dmaChannel, *videocore.Mem, error) {
|
|
if drvDMA.dmaMemory == nil {
|
|
return nil, nil, errors.New("bcm283x-dma is not initialized; try running as root?")
|
|
}
|
|
cb, buf, err := allocateCB(controlBlockSize + uint32Size) // CB + data
|
|
if err != nil {
|
|
return nil, nil, err
|
|
}
|
|
u := buf.Uint32()
|
|
offsetBytes := uint32(controlBlockSize)
|
|
u[offsetBytes/uint32Size] = 0x0
|
|
physBuf := uint32(buf.PhysAddr())
|
|
physBit := physBuf + offsetBytes
|
|
dest := drvDMA.pwmBaseAddr + 0x18 // PWM FIFO
|
|
if err := cb[0].initBlock(physBit, dest, uint32Size, false, true, false, false, dmaPWM); err != nil {
|
|
_ = buf.Close()
|
|
return nil, nil, err
|
|
}
|
|
cb[0].nextCB = physBuf // Loop back to self.
|
|
|
|
_, ch := pickChannel()
|
|
if ch == nil {
|
|
_ = buf.Close()
|
|
return nil, nil, errors.New("bcm283x-dma: no channel available")
|
|
}
|
|
ch.startIO(physBuf)
|
|
|
|
return ch, buf, nil
|
|
}
|
|
|
|
func startPWMbyDMA(p *Pin, rng, data uint32) (*dmaChannel, *videocore.Mem, error) {
|
|
if drvDMA.dmaMemory == nil {
|
|
return nil, nil, errors.New("bcm283x-dma is not initialized; try running as root?")
|
|
}
|
|
|
|
cb, buf, err := allocateCB(int(rng)*controlBlockSize + uint32Size) // rng CBs + mask
|
|
if err != nil {
|
|
return nil, nil, err
|
|
}
|
|
u := buf.Uint32()
|
|
offsetBytes := controlBlockSize * rng
|
|
u[offsetBytes/uint32Size] = uint32(1) << uint(p.number&31)
|
|
physBuf := uint32(buf.PhysAddr())
|
|
physBit := physBuf + offsetBytes
|
|
dest := [2]uint32{
|
|
drvGPIO.gpioBaseAddr + 0x28 + uint32Size*uint32(p.number/32), // clear
|
|
drvGPIO.gpioBaseAddr + 0x1C + uint32Size*uint32(p.number/32), // set
|
|
}
|
|
// High
|
|
ptr := physBuf
|
|
for i := uint32(0); i < data; i++ {
|
|
if err := cb[i].initBlock(physBit, dest[1], uint32Size, false, true, false, false, dmaPWM); err != nil {
|
|
_ = buf.Close()
|
|
return nil, nil, err
|
|
}
|
|
ptr += controlBlockSize
|
|
cb[i].nextCB = ptr
|
|
}
|
|
// Low
|
|
for i := data; i < rng; i++ {
|
|
|
|
if err := cb[i].initBlock(physBit, dest[0], uint32Size, false, true, false, false, dmaPWM); err != nil {
|
|
_ = buf.Close()
|
|
return nil, nil, err
|
|
}
|
|
ptr += controlBlockSize
|
|
cb[i].nextCB = ptr
|
|
|
|
}
|
|
cb[rng].nextCB = physBuf // Loop back to cb[0]
|
|
|
|
var blacklist []int
|
|
if rng*uint32Size >= 1<<16 {
|
|
// Don't use lite channels.
|
|
blacklist = []int{7, 8, 9, 10, 11, 12, 13, 14, 15}
|
|
}
|
|
_, ch := pickChannel(blacklist...)
|
|
|
|
if ch == nil {
|
|
_ = buf.Close()
|
|
return nil, nil, errors.New("bcm283x-dma: no channel available")
|
|
}
|
|
ch.startIO(physBuf)
|
|
|
|
return ch, buf, nil
|
|
}
|
|
|
|
// overSamples calculates the skip value which are the values that are read but
|
|
// discarded as the clock is too fast.
|
|
func overSamples(s gpiostream.Stream) (int, error) {
|
|
desired := s.Frequency()
|
|
skip := drvDMA.pwmDMAFreq / desired
|
|
if skip < 1 {
|
|
return 0, fmt.Errorf("frequency is too high(%s)", desired)
|
|
}
|
|
actualFreq := drvDMA.pwmDMAFreq / skip
|
|
errorPercent := 100 * (actualFreq - desired) / desired
|
|
if errorPercent < -10 || errorPercent > 10 {
|
|
return 0, fmt.Errorf("actual resolution differs more than 10%%(%s vs %s)", desired, actualFreq)
|
|
}
|
|
return int(skip), nil
|
|
}
|
|
|
|
// dmaReadStream streams input from a pin.
|
|
func dmaReadStream(p *Pin, b *gpiostream.BitStream) error {
|
|
skip, err := overSamples(b)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
if _, err := setPWMClockSource(); err != nil {
|
|
return err
|
|
}
|
|
|
|
// Needs 32x the memory since each read is one full uint32. On the other
|
|
// hand one could read 32 contiguous pins simultaneously at no cost.
|
|
// TODO(simokawa): Implement a function to get number of bits for all type of
|
|
// Stream
|
|
l := len(b.Bits) * 8 * uint32Size * int(skip)
|
|
// TODO(simokawa): Allocate multiple pages and CBs for huge buffer.
|
|
buf, err := drvDMA.dmaBufAllocator((l + 0xFFF) &^ 0xFFF)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer buf.Close()
|
|
cb, pCB, err := allocateCB(uint32Size)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer pCB.Close()
|
|
|
|
reg := drvGPIO.gpioBaseAddr + 0x34 + uint32Size*uint32(p.number/32) // GPIO Pin Level 0
|
|
if err := cb[0].initBlock(reg, uint32(buf.PhysAddr()), uint32(l), true, false, false, true, dmaPWM); err != nil {
|
|
return err
|
|
}
|
|
err = runIO(pCB, l <= maxLite)
|
|
uint32ToBitLSBF(b.Bits, buf.Bytes(), uint8(p.number&31), skip*uint32Size)
|
|
return err
|
|
}
|
|
|
|
// dmaWriteStreamEdges streams data to a pin as a half-duplex one controlBlock
|
|
// per bit toggle DMA stream.
|
|
//
|
|
// Memory usage is 32 bytes x number of bit changes rounded up to nearest
|
|
// 4Kb, so an arbitrary stream of 1s or 0s only takes 4Kb but a stream of
|
|
// 101010s will takes 256x the memory.
|
|
//
|
|
// TODO(maruel): Use huffman-coding-like repeated patterns detection to
|
|
// "compress" the bitstream. This trades off upfront computation for lower
|
|
// memory usage. The "compressing" function should be public, so the user can
|
|
// call it only once yet stream multiple times.
|
|
//
|
|
// TODO(maruel): Mutate the program as it goes to reduce duplication by having
|
|
// the DMA controller write in a following controlBlock.nextCB.
|
|
// handling gpiostream.Program explicitly.
|
|
func dmaWriteStreamEdges(p *Pin, w gpiostream.Stream) error {
|
|
d := w.Duration()
|
|
if d == 0 {
|
|
return nil
|
|
}
|
|
var bits []byte
|
|
var msb bool
|
|
switch v := w.(type) {
|
|
case *gpiostream.BitStream:
|
|
bits = v.Bits
|
|
msb = !v.LSBF
|
|
default:
|
|
return fmt.Errorf("unknown type: %T", v)
|
|
}
|
|
skip, err := overSamples(w)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
|
|
// Calculate the number of controlBlock needed.
|
|
count := 1
|
|
stride := uint32(skip)
|
|
last := getBit(bits[0], 0, msb)
|
|
l := int(int64(d) * int64(w.Frequency()) / int64(physic.Hertz)) // Bits
|
|
for i := 1; i < l; i++ {
|
|
if v := getBit(bits[i/8], i%8, msb); v != last || stride == maxLite {
|
|
last = v
|
|
count++
|
|
stride = 0
|
|
}
|
|
stride += uint32(skip)
|
|
}
|
|
// 32 bytes for each CB and 4 bytes for the mask.
|
|
bufBytes := count*controlBlockSize + uint32Size
|
|
cb, buf, err := allocateCB((bufBytes + 0xFFF) &^ 0xFFF)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer buf.Close()
|
|
|
|
// Setup the single mask buffer of 4Kb.
|
|
mask := uint32(1) << uint(p.number&31)
|
|
u := buf.Uint32()
|
|
offset := (len(buf.Bytes()) - uint32Size)
|
|
u[offset/uint32Size] = mask
|
|
physBit := uint32(buf.PhysAddr()) + uint32(offset)
|
|
|
|
// Other constants during the loop.
|
|
// Waits does not seem to work as expected. Not counted as DREQ pulses?
|
|
// Use PWM's rng1 instead for this.
|
|
//waits := divs - 1
|
|
dest := [2]uint32{
|
|
drvGPIO.gpioBaseAddr + 0x28 + uint32Size*uint32(p.number/32), // clear
|
|
drvGPIO.gpioBaseAddr + 0x1C + uint32Size*uint32(p.number/32), // set
|
|
}
|
|
|
|
// Render the controlBlock's to trigger the bit trigger for either Set or
|
|
// Clear GPIO memory registers.
|
|
last = getBit(bits[0], 0, msb)
|
|
index := 0
|
|
stride = uint32(skip)
|
|
for i := 1; i < l; i++ {
|
|
if v := getBit(bits[i/8], i%8, msb); v != last || stride == maxLite {
|
|
if err := cb[index].initBlock(physBit, dest[last], stride*uint32Size, false, true, false, false, dmaPWM); err != nil {
|
|
return err
|
|
}
|
|
// It is not necessary to use physToUncachedPhys() here.
|
|
cb[index].nextCB = uint32(buf.PhysAddr()) + controlBlockSize*uint32(index+1)
|
|
index++
|
|
stride = 0
|
|
last = v
|
|
}
|
|
stride += uint32(skip)
|
|
}
|
|
if err := cb[index].initBlock(physBit, dest[last], stride*uint32Size, false, true, false, false, dmaPWM); err != nil {
|
|
return err
|
|
}
|
|
|
|
// Start clock before DMA
|
|
_, err = setPWMClockSource()
|
|
if err != nil {
|
|
return err
|
|
}
|
|
return runIO(buf, true)
|
|
}
|
|
|
|
// dmaWriteStreamDualChannel streams data to a pin using two DMA channels.
|
|
//
|
|
// In practice this leads to a glitchy stream.
|
|
func dmaWriteStreamDualChannel(p *Pin, w gpiostream.Stream) error {
|
|
// TODO(maruel): Analyse 'w' to figure out the programs to load, and create
|
|
// the number of controlBlock needed to reduce memory usage.
|
|
// TODO(maruel): When only one channel is needed, it is much more memory
|
|
// efficient to use DMA to write to PWM FIFO.
|
|
skip, err := overSamples(w)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
// Calculates the number of needed bytes.
|
|
l := int(int64(w.Duration())*int64(w.Frequency())/int64(physic.Hertz)) * skip * uint32Size
|
|
bufLen := (l + 0xFFF) &^ 0xFFF
|
|
bufSet, err := drvDMA.dmaBufAllocator(bufLen)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer bufSet.Close()
|
|
bufClear, err := drvDMA.dmaBufAllocator(bufLen)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer bufClear.Close()
|
|
cb, pCB, err := allocateCB(4096)
|
|
if err != nil {
|
|
return err
|
|
}
|
|
defer pCB.Close()
|
|
|
|
// Needs 64x the memory since each write is 2 full uint32. On the other
|
|
// hand one could write 32 contiguous pins simultaneously at no cost.
|
|
mask := uint32(1) << uint(p.number&31)
|
|
if err := raster32(w, skip, bufClear.Uint32(), bufSet.Uint32(), mask); err != nil {
|
|
return err
|
|
}
|
|
|
|
// Start clock before DMA start
|
|
_, err = setPWMClockSource()
|
|
if err != nil {
|
|
return err
|
|
}
|
|
|
|
regSet := drvGPIO.gpioBaseAddr + 0x1C + uint32Size*uint32(p.number/32)
|
|
if err := cb[0].initBlock(uint32(bufSet.PhysAddr()), regSet, uint32(l), false, true, true, false, dmaPWM); err != nil {
|
|
return err
|
|
}
|
|
regClear := drvGPIO.gpioBaseAddr + 0x28 + uint32Size*uint32(p.number/32)
|
|
if err := cb[1].initBlock(uint32(bufClear.PhysAddr()), regClear, uint32(l), false, true, true, false, dmaPWM); err != nil {
|
|
return err
|
|
}
|
|
|
|
// The first channel must be a full bandwidth one. The "light" ones are
|
|
// effectively a single one, which means that they are interleaved. If both
|
|
// are "light" then the jitter is largely increased.
|
|
x, chSet := pickChannel(6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
|
|
if chSet == nil {
|
|
return errors.New("bcm283x-dma: no channel available")
|
|
}
|
|
defer chSet.reset()
|
|
_, chClear := pickChannel(x)
|
|
if chClear == nil {
|
|
return errors.New("bcm283x-dma: no secondary channel available")
|
|
}
|
|
defer chClear.reset()
|
|
|
|
// Two channel need to be synchronized but there is not such a mechanism.
|
|
chSet.startIO(uint32(pCB.PhysAddr())) // cb[0]
|
|
chClear.startIO(uint32(pCB.PhysAddr()) + controlBlockSize) // cb[1]
|
|
|
|
err1 := chSet.wait()
|
|
err2 := chClear.wait()
|
|
if err1 == nil {
|
|
return err2
|
|
}
|
|
return err1
|
|
}
|
|
|
|
// physToUncachedPhys returns the uncached physical memory address backing a
|
|
// physical memory address.
|
|
//
|
|
// p must be rooted at a page boundary (4096).
|
|
func physToUncachedPhys(p uint32) uint32 {
|
|
// http://en.wikibooks.org/wiki/Aros/Platforms/Arm_Raspberry_Pi_support#Framebuffer
|
|
return p | drvGPIO.dramBus
|
|
}
|
|
|
|
func physToBus(p uint32) uint32 {
|
|
return (p & periphMask) | periphBus
|
|
}
|
|
|
|
// smokeTest allocates two physical pages, ask the DMA controller to copy the
|
|
// data from one page to another and make sure the content is as expected.
|
|
//
|
|
// This should take a fraction of a second and will make sure the driver is
|
|
// usable. This ensures there's at least one DMA channel available.
|
|
func smokeTest() error {
|
|
// If these are commented out due to a new processor having different
|
|
// characteristics, the corresponding code needs to be updated.
|
|
if drvDMA.dmaMemory.channels[6].debug&dmaLite != 0 {
|
|
return errors.New("unexpected hardware: DMA channel #6 shouldn't be lite")
|
|
}
|
|
if drvDMA.dmaMemory.channels[7].debug&dmaLite == 0 {
|
|
return errors.New("unexpected hardware: DMA channel #7 should be lite")
|
|
}
|
|
if drvDMA.dmaMemory.enable != 0x7FFF {
|
|
return errors.New("unexpected hardware: DMA enable is not fully set")
|
|
}
|
|
|
|
const size = 4096 * uint32Size // 16kb
|
|
const holeSize = 1 // Minimum DMA alignment
|
|
|
|
alloc := func(s int) (pmem.Mem, error) {
|
|
return videocore.Alloc(s)
|
|
}
|
|
|
|
copyMem := func(pDst, pSrc uint64) error {
|
|
// Allocate a control block and initialize it.
|
|
pCB, err2 := videocore.Alloc(4096)
|
|
if err2 != nil {
|
|
return err2
|
|
}
|
|
defer pCB.Close()
|
|
var cb *controlBlock
|
|
if err := pCB.AsPOD(&cb); err != nil {
|
|
return err
|
|
}
|
|
if false {
|
|
// This code is not run by default because it resets the PWM clock on
|
|
// process startup, which may cause undesirable glitches.
|
|
|
|
// Initializes the PWM clock right away to 1MHz.
|
|
_, err := setPWMClockSource()
|
|
if err != nil {
|
|
return err
|
|
}
|
|
if err := cb.initBlock(uint32(pSrc), uint32(pDst)+holeSize, size-2*holeSize, false, false, true, true, dmaPWM); err != nil {
|
|
return err
|
|
}
|
|
} else {
|
|
// Use maximum performance.
|
|
if err := cb.initBlock(uint32(pSrc), uint32(pDst)+holeSize, size-2*holeSize, false, false, true, true, dmaFire); err != nil {
|
|
return err
|
|
}
|
|
}
|
|
return runIO(pCB, size-2*holeSize <= maxLite)
|
|
}
|
|
|
|
return pmem.TestCopy(size, holeSize, alloc, copyMem)
|
|
}
|
|
|
|
// driverDMA implements periph.Driver.
|
|
//
|
|
// It implements much more than the DMA controller, it also exposes the clocks,
|
|
// the PWM and PCM controllers.
|
|
type driverDMA struct {
|
|
pcmBaseAddr uint32
|
|
pwmBaseAddr uint32
|
|
|
|
dmaMemory *dmaMap
|
|
dmaChannel15 *dmaChannel
|
|
pcmMemory *pcmMap
|
|
clockMemory *clockMap
|
|
timerMemory *timerMap
|
|
gpioPadMemory *gpioPadMap
|
|
// Page 138
|
|
// - Two independent bit-streams
|
|
// - Each channel either a PWM or serialised version of a 32-bit word
|
|
// - Variable input and output resolutions.
|
|
// - Load data from a FIFO storage block, to extent to 8 32-bit words (256
|
|
// bits).
|
|
//
|
|
// Author note: 100Mhz base resolution with a 256 bits 1-bit stream is
|
|
// actually good enough to generate a DAC.
|
|
pwmMemory *pwmMap
|
|
|
|
// These clocks are shared with hardware PWM, DMA driven PWM and BitStream.
|
|
pwmBaseFreq physic.Frequency
|
|
pwmDMAFreq physic.Frequency
|
|
pwmDMACh *dmaChannel
|
|
pwmDMABuf *videocore.Mem
|
|
|
|
// dmaBufAllocator is overridden for unit testing.
|
|
dmaBufAllocator func(s int) (*videocore.Mem, error) // Set to videocore.Alloc
|
|
}
|
|
|
|
func (d *driverDMA) Close() error {
|
|
// TODO(maruel): Stop DMA and PWM controllers.
|
|
d.pcmBaseAddr = 0
|
|
d.pwmBaseAddr = 0
|
|
d.dmaMemory = nil
|
|
d.dmaChannel15 = nil
|
|
d.pcmMemory = nil
|
|
d.clockMemory = nil
|
|
d.timerMemory = nil
|
|
d.pwmMemory = nil
|
|
d.pwmBaseFreq = 0
|
|
d.pwmDMAFreq = 0
|
|
d.pwmDMACh = nil
|
|
d.pwmDMABuf = nil
|
|
d.dmaBufAllocator = nil
|
|
return nil
|
|
}
|
|
|
|
func (d *driverDMA) String() string {
|
|
return "bcm283x-dma"
|
|
}
|
|
|
|
func (d *driverDMA) Prerequisites() []string {
|
|
return []string{"bcm283x-gpio"}
|
|
}
|
|
|
|
func (d *driverDMA) After() []string {
|
|
return nil
|
|
}
|
|
|
|
func (d *driverDMA) Init() (bool, error) {
|
|
d.dmaBufAllocator = videocore.Alloc
|
|
d.pwmBaseFreq = 25 * physic.MegaHertz
|
|
d.pwmDMAFreq = 200 * physic.KiloHertz
|
|
// baseAddr is initialized by prerequisite driver bcm283x-gpio.
|
|
if err := pmem.MapAsPOD(uint64(drvGPIO.baseAddr+0x7000), &d.dmaMemory); err != nil {
|
|
if os.IsPermission(err) {
|
|
return true, fmt.Errorf("need more access, try as root: %v", err)
|
|
}
|
|
return true, err
|
|
}
|
|
// Channel #15 is "physically removed from the other DMA Channels so it has a
|
|
// different address base".
|
|
if err := pmem.MapAsPOD(uint64(drvGPIO.baseAddr+0xE05000), &d.dmaChannel15); err != nil {
|
|
return true, err
|
|
}
|
|
d.pcmBaseAddr = drvGPIO.baseAddr + 0x203000
|
|
if err := pmem.MapAsPOD(uint64(d.pcmBaseAddr), &d.pcmMemory); err != nil {
|
|
return true, err
|
|
}
|
|
d.pwmBaseAddr = drvGPIO.baseAddr + 0x20C000
|
|
if err := pmem.MapAsPOD(uint64(d.pwmBaseAddr), &d.pwmMemory); err != nil {
|
|
return true, err
|
|
}
|
|
if err := pmem.MapAsPOD(uint64(drvGPIO.baseAddr+0x101000), &d.clockMemory); err != nil {
|
|
return true, err
|
|
}
|
|
if err := pmem.MapAsPOD(uint64(drvGPIO.baseAddr+0x3000), &d.timerMemory); err != nil {
|
|
return true, err
|
|
}
|
|
if err := pmem.MapAsPOD(uint64(drvGPIO.baseAddr+0x100000), &d.gpioPadMemory); err != nil {
|
|
return true, err
|
|
}
|
|
// Do not run smokeTest() unless it's clear it is not dangerous.
|
|
return true, nil
|
|
}
|
|
|
|
func debugDMA() {
|
|
for i, ch := range drvDMA.dmaMemory.channels {
|
|
log.Println(i, ch.cs.String())
|
|
if ch.cs&dmaActive != 0 {
|
|
log.Printf("%x: %s", ch.cbAddr, ch.GoString())
|
|
}
|
|
}
|
|
log.Println(15, drvDMA.dmaChannel15.cs.String())
|
|
}
|
|
|
|
func resetDMA(ch int) error {
|
|
if ch < len(drvDMA.dmaMemory.channels) {
|
|
drvDMA.dmaMemory.channels[ch].reset()
|
|
} else if ch == 15 {
|
|
drvDMA.dmaChannel15.reset()
|
|
} else {
|
|
return fmt.Errorf("invalid dma channel %d", ch)
|
|
}
|
|
return nil
|
|
}
|
|
|
|
func init() {
|
|
if isArm {
|
|
periph.MustRegister(&drvDMA)
|
|
}
|
|
}
|
|
|
|
var drvDMA driverDMA
|