273 lines
12 KiB
Go
273 lines
12 KiB
Go
// Copyright 2017 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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package bcm283x
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import (
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"errors"
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"fmt"
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"time"
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"periph.io/x/conn/v3/physic"
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)
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// PWENi is used to enable/disable the corresponding channel. Setting this bit
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// to 1 enables the channel and transmitter state machine. All registers and
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// FIFO is writable without setting this bit.
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//
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// MODEi bit is used to determine mode of operation. Setting this bit to 0
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// enables PWM mode. In this mode data stored in either PWM_DATi or FIFO is
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// transmitted by pulse width modulation within the range defined by PWM_RNGi.
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// When this mode is used MSENi defines whether to use PWM algorithm. Setting
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// MODEi to 1 enables serial mode, in which data stored in either PWM_DATi or
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// FIFO is transmitted serially within the range defined by PWM_RNGi. Data is
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// transmitted MSB first and truncated or zeropadded depending on PWM_RNGi.
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// Default mode is PWM.
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//
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// RPTLi is used to enable/disable repeating of the last data available in the
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// FIFO just before it empties. When this bit is 1 and FIFO is used, the last
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// available data in the FIFO is repeatedly sent. This may be useful in PWM
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// mode to avoid duty cycle gaps. If the FIFO is not used this bit does not
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// have any effect. Default operation is do-notrepeat.
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//
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// SBITi defines the state of the output when no transmission takes place. It
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// also defines the zero polarity for the zero padding in serialiser mode. This
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// bit is padded between two consecutive transfers as well as tail of the data
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// when PWM_RNGi is larger than bit depth of data being transferred. this bit
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// is zero by default.
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//
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// POLAi is used to configure the polarity of the output bit. When set to high
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// the final output is inverted. Default operation is no inversion.
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//
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// USEFi bit is used to enable/disable FIFO transfer. When this bit is high
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// data stored in the FIFO is used for transmission. When it is low, data
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// written to PWM_DATi is transferred. This bit is 0 as default.
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//
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// CLRF is used to clear the FIFO. Writing a 1 to this bit clears the FIFO.
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// Writing 0 has no effect. This is a single shot operation and reading the bit
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// always returns 0.
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//
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// MSENi is used to determine whether to use PWM algorithm or simple M/S ratio
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// transmission. When this bit is high M/S transmission is used. This bit is
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// zero as default. When MODEi is 1, this configuration bit has no effect.
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//
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// See page 139-140 for the description of the PWM and M/S ratio algorithms.
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const (
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// 31:16 reserved
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pwm2MS pwmControl = 1 << 15 // MSEN2; 0: PWM algorithm is used; 1: M/S transmission is used
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// 14 reserved
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pwm2UseFIFO pwmControl = 1 << 13 // USEF2; 0: Data register is transmitted; 1: Fifo is used for transmission
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pwm2Polarity pwmControl = 1 << 12 // POLA2; 0: 0=low 1=high; 1: 1=low 0=high
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pwm2SilenceHigh pwmControl = 1 << 11 // SBIT2; Defines the state of the output when no transmission takes place
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pwm2RepeatLastData pwmControl = 1 << 10 // RPTL2; 0: Transmission interrupts when FIFO is empty; 1: Last data in FIFO is transmitted repetedly until FIFO is not empty
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pwm2Serialiser pwmControl = 1 << 9 // MODE2; 0: PWM mode; 1: Serialiser mode
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pwm2Enable pwmControl = 1 << 8 // PWEN2; Enable channel 2
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pwm2Mask pwmControl = pwm2MS | pwm2UseFIFO | pwm2Polarity | pwm2SilenceHigh | pwm2RepeatLastData | pwm2Serialiser | pwm2Enable
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pwm1MS pwmControl = 1 << 7 // MSEN1; 0: PWM algorithm is used; 1: M/S transmission is used
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pwmClearFIFO pwmControl = 1 << 6 // CLRF1; Clear the fifo
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pwm1UseFIFO pwmControl = 1 << 5 // USEF1; 0: Data register is transmitted; 1: Fifo is used for transmission
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pwm1Polarity pwmControl = 1 << 4 // POLA1; 0: 0=low 1=high; 1: 1=low 0=high
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pwm1SilenceHigh pwmControl = 1 << 3 // SBIT1; Defines the state of the output when no transmission takes place
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pwm1RepeatLastData pwmControl = 1 << 2 // RPTL1; 0: Transmission interrupts when FIFO is empty; 1: Last data in FIFO is transmitted repetedly until FIFO is not empty
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pwm1Serialiser pwmControl = 1 << 1 // MODE1; 0: PWM mode; 1: Serialiser mode
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pwm1Enable pwmControl = 1 << 0 // PWEN1; Enable channel 1
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pwm1Mask pwmControl = pwm1MS | pwm1UseFIFO | pwm1Polarity | pwm1SilenceHigh | pwm1RepeatLastData | pwm1Serialiser | pwm1Enable
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)
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// Pages 141-143.
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type pwmControl uint32
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const (
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// 31:13 reserved
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// STAi bit indicates the current state of the channel which is useful for
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// debugging purposes. The bit set means the channel is currently
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// transmitting data.
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pwmSta4 pwmStatus = 1 << 12 // STA4
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pwmSta3 pwmStatus = 1 << 11 // STA3
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pwmSta2 pwmStatus = 1 << 10 // STA2
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pwmSta1 pwmStatus = 1 << 9 // STA1
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// BERR sets to high when an error has occurred while writing to registers
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// via APB. This may happen if the bus tries to write successively to same
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// set of registers faster than the synchroniser block can cope with.
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// Multiple switching may occur and contaminate the data during
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// synchronisation. Software should clear this bit by writing 1. Writing 0
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// to this bit has no effect.
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pwmBusErr pwmStatus = 1 << 8 // BERR Bus Error flag
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// GAPOi. bit indicates that there has been a gap between transmission of two
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// consecutive data from FIFO. This may happen when FIFO gets empty after
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// state machine has sent a word and waits for the next. If control bit RPTLi
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// is set to high this event will not occur. Software must clear this bit by
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// writing 1. Writing 0 to this bit has no effect.
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pwmGapo4 pwmStatus = 1 << 7 // GAPO4 Channel 4 Gap Occurred flag
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pwmGapo3 pwmStatus = 1 << 6 // GAPO3 Channel 3 Gap Occurred flag
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pwmGapo2 pwmStatus = 1 << 5 // GAPO2 Channel 2 Gap Occurred flag
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pwmGapo1 pwmStatus = 1 << 4 // GAPO1 Channel 1 Gap Occurred flag
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// RERR1 bit sets to high when a read when empty error occurs. Software must
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// clear this bit by writing 1. Writing 0 to this bit has no effect.
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pwmRerr1 pwmStatus = 1 << 3 // RERR1
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// WERR1 bit sets to high when a write when full error occurs. Software must
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// clear this bit by writing 1. Writing 0 to this bit has no effect.
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pwmWerr1 pwmStatus = 1 << 2 // WERR1
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// EMPT1 bit indicates the empty status of the FIFO. If this bit is high FIFO
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// is empty.
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pwmEmpt1 pwmStatus = 1 << 1 // EMPT1
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// FULL1 bit indicates the full status of the FIFO. If this bit is high FIFO
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// is full.
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pwmFull1 pwmStatus = 1 << 0 // FULL1
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pwmStatusMask = pwmSta4 | pwmSta3 | pwmSta2 | pwmSta1 | pwmBusErr | pwmGapo4 | pwmGapo3 | pwmGapo2 | pwmGapo1 | pwmRerr1 | pwmWerr1 | pwmEmpt1 | pwmFull1
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)
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// Pages 144-145.
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type pwmStatus uint32
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const (
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pwmDMAEnable pwmDMACfg = 1 << 31 // ENAB
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// 30:16 reserved
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pwmPanicShift = 16
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pwmPanicMask pwmDMACfg = 0xFF << pwmPanicShift // PANIC Default is 7
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pwmDreqMask pwmDMACfg = 0xFF // DREQ Default is 7
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)
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// Page 145.
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type pwmDMACfg uint32
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// pwmMap is the block to control the PWM generator.
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//
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// Note that pins are named PWM0 and PWM1 but the mapping uses channel numbers
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// 1 and 2.
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// - PWM0: GPIO12, GPIO18, GPIO40, GPIO52.
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// - PWM1: GPIO13, GPIO19, GPIO41, GPIO45, GPIO53.
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//
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// Each channel works independently. They can either output a bitstream or a
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// serialised version of up to eight 32 bits words.
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//
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// The default base PWM frequency is 100Mhz.
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//
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// Description at page 138-139.
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//
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// Page 140-141.
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type pwmMap struct {
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ctl pwmControl // CTL
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status pwmStatus // STA
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dmaCfg pwmDMACfg // DMAC
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// This register is used to define the range for the corresponding channel.
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// In PWM mode evenly distributed pulses are sent within a period of length
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// defined by this register. In serial mode serialised data is transmitted
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// within the same period. If the value in PWM_RNGi is less than 32, only the
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// first PWM_RNGi bits are sent resulting in a truncation. If it is larger
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// than 32 excess zero bits are padded at the end of data. Default value for
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// this register is 32.
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dummy1 uint32 // Padding
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rng1 uint32 // RNG1
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// This register stores the 32 bit data to be sent by the PWM Controller when
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// USEFi is 0. In PWM mode data is sent by pulse width modulation: the value
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// of this register defines the number of pulses which is sent within the
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// period defined by PWM_RNGi. In serialiser mode data stored in this
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// register is serialised and transmitted.
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dat1 uint32 // DAT1
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// This register is the FIFO input for the all channels. Data written to this
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// address is stored in channel FIFO and if USEFi is enabled for the channel
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// i it is used as data to be sent. This register is write only, and reading
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// this register will always return bus default return value, pwm0.
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// When more than one channel is enabled for FIFO usage, the data written
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// into the FIFO is shared between these channels in turn. For example if the
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// word series A B C D E F G H I .. is written to FIFO and two channels are
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// active and configured to use FIFO then channel 1 will transmit words A C E
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// G I .. and channel 2 will transmit words B D F H .. . Note that
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// requesting data from the FIFO is in locked-step manner and therefore
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// requires tight coupling of state machines of the channels. If any of the
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// channel range (period) value is different than the others this will cause
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// the channels with small range values to wait between words hence resulting
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// in gaps between words. To avoid that, each channel sharing the FIFO should
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// be configured to use the same range value. Also note that RPTLi are not
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// meaningful when the FIFO is shared between channels as there is no defined
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// channel to own the last data in the FIFO. Therefore sharing channels must
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// have their RPTLi set to zero.
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//
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// If the set of channels to share the FIFO has been modified after a
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// configuration change, FIFO should be cleared before writing new data.
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fifo uint32 // FIF1
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dummy2 uint32 // Padding
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rng2 uint32 // RNG2 Equivalent of rng1 for channel 2
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dat2 uint32 // DAT2 Equivalent of dat1 for channel 2
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}
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// reset stops the PWM.
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func (p *pwmMap) reset() {
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p.dmaCfg = 0
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p.ctl |= pwmClearFIFO
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p.ctl &^= pwm1Enable | pwm2Enable
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Nanospin(100 * time.Microsecond) // Cargo cult copied. Probably not necessary.
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p.status = pwmBusErr | pwmGapo1 | pwmGapo2 | pwmGapo3 | pwmGapo4 | pwmRerr1 | pwmWerr1
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Nanospin(100 * time.Microsecond)
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// Use the full 32 bits of DATi.
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p.rng1 = 32
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p.rng2 = 32
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}
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// setPWMClockSource sets the PWM clock for use by the DMA controller for
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// pacing.
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//
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// It may select an higher frequency than the one requested.
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//
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// Other potentially good clock sources are PCM, SPI and UART.
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func setPWMClockSource() (physic.Frequency, error) {
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if drvDMA.pwmMemory == nil {
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return 0, errors.New("subsystem PWM not initialized")
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}
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if drvDMA.clockMemory == nil {
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return 0, errors.New("subsystem Clock not initialized")
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}
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if drvDMA.pwmDMACh != nil {
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// Already initialized
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return drvDMA.pwmDMAFreq, nil
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}
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// divs * div must fit in rng1 registor.
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div := uint32(drvDMA.pwmBaseFreq / drvDMA.pwmDMAFreq)
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actual, divs, err := drvDMA.clockMemory.pwm.set(drvDMA.pwmBaseFreq, div)
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if err != nil {
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return 0, err
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}
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if e := actual / physic.Frequency(divs*div); drvDMA.pwmDMAFreq != e {
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return 0, fmt.Errorf("unexpected DMA frequency %s != %s (%d/%d/%d)", drvDMA.pwmDMAFreq, e, actual, divs, div)
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}
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// It acts as a clock multiplier, since this amount of data is sent per
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// clock tick.
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drvDMA.pwmMemory.rng1 = divs * div
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Nanospin(10 * time.Microsecond)
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// Periph data (?)
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// Use low priority.
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drvDMA.pwmMemory.dmaCfg = pwmDMAEnable | pwmDMACfg(15<<pwmPanicShift|15)
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Nanospin(10 * time.Microsecond)
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drvDMA.pwmMemory.ctl |= pwmClearFIFO
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Nanospin(10 * time.Microsecond)
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old := drvDMA.pwmMemory.ctl
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drvDMA.pwmMemory.ctl = (old & ^pwmControl(0xff)) | pwm1UseFIFO | pwm1Enable
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// Start DMA
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if drvDMA.pwmDMACh, drvDMA.pwmDMABuf, err = dmaWritePWMFIFO(); err != nil {
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return 0, err
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}
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return drvDMA.pwmDMAFreq, nil
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}
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func resetPWMClockSource() error {
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if drvDMA.pwmDMACh != nil {
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drvDMA.pwmDMACh.reset()
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drvDMA.pwmDMACh = nil
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}
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if drvDMA.pwmDMABuf != nil {
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if err := drvDMA.pwmDMABuf.Close(); err != nil {
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return err
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}
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drvDMA.pwmDMABuf = nil
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}
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_, _, err := drvDMA.clockMemory.pwm.set(0, 0)
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return err
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}
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